On Wed, May 15, 2002 at 12:33:46AM +0100, Jos� Fonseca wrote: > I've been making some tests to the bus mastering in Mach64 chip as I told > yesterday on IRC. Since this was discussed pretty late I would like to > briefly document to the others DRI developers what I'm trying to do: > > > Since there is no way of caching DMA buffers on the Mach64 chip (is is > done via the CCE on Rage128, or the primary DMA buffer in Matrox) nor to > get notification when it's done, appearantly the only way left would be to > poll (either when new buffers were received by the DRM from the client, or > on a constant time interrupt such as VBLANK). This means the engine could > be stopped quite often yielding lower preformance. > > A last resource alternative is to modify the descriptor table which > hold pointers to 4k DMA buffers blocks and add to it _while_ the engine is > running, and trying to resolve the resulting race condition with buffer > aging. The following tests try to access the possibility or not of that > scheme.
This is just a crazy suggestion, but has anybody talked to any ATI engineers to find out how they do it in win32? Your idea sounds very good, but I'd still be curious to hear how (or if!) ATI solved this problem on Windows... -- Tell that to the Marines! _______________________________________________________________ Have big pipes? SourceForge.net is looking for download mirrors. We supply the hardware. You get the recognition. Email Us: [EMAIL PROTECTED] _______________________________________________ Dri-devel mailing list [EMAIL PROTECTED] https://lists.sourceforge.net/lists/listinfo/dri-devel
