>Thanks, that's what I needed to know. One last question - would you know >whether Radeon AGP has a restriction of not being able to DMA into non-AGP >memory ? I am providing a table with physical addresses and all, but >transfers below 0x4000000 fail - and this is the value written in >CP_RB_BASE, which also coincides with statement from agpgart that only >439mb out of 512 are available for agp memory. Is there a way to query >agpgart about which memory is agp without acquiring it ?
Are you sure your radeon memory controller hasn't anything else mapped to below 0x4000000 ? (like the frame buffer). AFAIK, Radeon will do perfectly normal bus master from any address not colliding with either MC_FB_LOCATION or MC_AGP_LOCATION. That's a reason why I beleive we should hack the driver to always remap MC_FB_LOCATION to match the bus address of the frame buffer as seen from the PCI. Currently, at least on pmacs, we set MC_FB_LOCATION so that the framebuffer is at address 0 in card space. If we also take care of putting the AGP aperture in such a location where it won't collide with RAM, the entire machine memory will be available to normal bus master. I've done some experiments moving MC_FB_LOCATION around on my tipb (Radeon M6) but mostly obtained hard card lockups, I beleive that value can't just be moved alone. We must obviously move DISPLAY_BASE_ADDR (and it's equivalent for CRTC2), some surface regs, and probably a few others. The doc isn't always clear about what registers are absolute addresses in card space, and what are offsets relative to MC_FB_LOCATION. Ben. _______________________________________________ Dri-devel mailing list [EMAIL PROTECTED] https://lists.sourceforge.net/lists/listinfo/dri-devel
