On 7/5/26 10:14 AM, Akhil P Oommen wrote: > From: Puranam V G Tejaswi <[email protected]> > > The RBBM_CLOCK_CNTL3_TP0 entry in a730_hwcg has bits[19:16] set to 2 > (clock gating enabled for that TP0 stage). As per the latest > recommendation, clear this nibble to disable clock gating for this > particular stage. > > Fixes: 9588d2f860a4 ("drm/msm/a6xx: Add A730 support") > Signed-off-by: Puranam V G Tejaswi <[email protected]> > Signed-off-by: Akhil P Oommen <[email protected]> > ---
Reviewed-by: Konrad Dybcio <[email protected]> Konrad
