Newer Adreno GPUs expose more than 16 GX frequency levels. Introduce HFI_MAX_GX_LEVELS and use it to size the perf-table and bandwidth-table GX vote arrays, and to derive GMU_MAX_GX_FREQS, so these levels are not truncated.
Signed-off-by: Akhil P Oommen <[email protected]> --- drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 2 +- drivers/gpu/drm/msm/adreno/a6xx_hfi.h | 7 ++++--- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h index 3f96b10b5f61..62e3fb230cd3 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h @@ -20,7 +20,7 @@ struct a6xx_gmu_bo { u64 iova; }; -#define GMU_MAX_GX_FREQS 32 +#define GMU_MAX_GX_FREQS HFI_MAX_GX_LEVELS #define GMU_MAX_CX_FREQS 6 #define GMU_MAX_BCMS 3 diff --git a/drivers/gpu/drm/msm/adreno/a6xx_hfi.h b/drivers/gpu/drm/msm/adreno/a6xx_hfi.h index e10d32ce93e0..f4da73a555c6 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_hfi.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_hfi.h @@ -5,6 +5,7 @@ #define _A6XX_HFI_H_ #define HFI_MAX_QUEUES 3 +#define HFI_MAX_GX_LEVELS 24 struct a6xx_hfi_queue_table_header { u32 version; @@ -119,7 +120,7 @@ struct a6xx_hfi_msg_perf_table_v1 { u32 num_gpu_levels; u32 num_gmu_levels; - struct perf_level gx_votes[16]; + struct perf_level gx_votes[HFI_MAX_GX_LEVELS]; struct perf_level cx_votes[4]; } __packed; @@ -128,7 +129,7 @@ struct a6xx_hfi_msg_perf_table { u32 num_gpu_levels; u32 num_gmu_levels; - struct perf_gx_level gx_votes[16]; + struct perf_gx_level gx_votes[HFI_MAX_GX_LEVELS]; struct perf_level cx_votes[4]; } __packed; @@ -144,7 +145,7 @@ struct a6xx_hfi_msg_bw_table { u32 cnoc_cmds_addrs[6]; u32 cnoc_cmds_data[2][6]; u32 ddr_cmds_addrs[8]; - u32 ddr_cmds_data[16][8]; + u32 ddr_cmds_data[HFI_MAX_GX_LEVELS][8]; } __packed; #define HFI_H2F_MSG_TEST 5 -- 2.54.0
