[WHY] In the evolution of displays from DP 1.4 to DP 2.0, due to considerations some factors,such as cost, some displays support 128b/132b encoding but do not support UHBR rate transmission. The values can be read from DPCD register address as below.
0x00006 is 03 0x02215 is 00 For such displays, the current kernel reports the following error message. [drm:dp_retrieve_lttpr_cap [amdgpu]] *ERROR* retrieve_link_cap: Invalid RX 128b_132b_supported_link_rates [HOW] Add new judgment: if all bits in dp_128b_132b_supported_link_rates.raw are non-zero, then further determine the specific UHBR type; otherwise, determine that the display does not support UHBR. Signed-off-by: Jackie Dong <[email protected]> --- .../gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c index 47abb4066709..58cbb7ac8f9e 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c @@ -2079,7 +2079,8 @@ static bool retrieve_link_cap(struct dc_link *link) if (!dpcd_read_sink_ext_caps(link)) link->dpcd_sink_ext_caps.raw = 0; - if (link->dpcd_caps.channel_coding_cap.bits.DP_128b_132b_SUPPORTED) { + if (link->dpcd_caps.channel_coding_cap.bits.DP_128b_132b_SUPPORTED && + link->dpcd_caps.dp_128b_132b_supported_link_rates.raw) { DC_LOG_DP2("128b/132b encoding is supported at link %d", link->link_index); /* Read 128b/132b suppoerted link rates */ -- 2.43.0
