The verisilicon,dc binding was originally written for the T-Head TH1520 SoC carrying a DC8200, and hard-codes five clocks, three resets and two output ports.
Add the Nuvoton MA35D1 DCUltraLite (nuvoton,ma35d1-dcu) to the binding. The DCUltraLite uses only two clocks (core, pix0) and one reset (core), with a single output port. Use allOf/if blocks to express per-variant constraints rather than hard-coding the DC8200 topology at the top level. Each compatible's block constrains the clock and reset item counts; the nuvoton block additionally overrides clock-names to the two names it actually uses. Signed-off-by: Joey Lu <[email protected]> --- .../bindings/display/verisilicon,dc.yaml | 57 +++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/Documentation/devicetree/bindings/display/verisilicon,dc.yaml b/Documentation/devicetree/bindings/display/verisilicon,dc.yaml index 9dc35ab973f2..1e751f3c7ce8 100644 --- a/Documentation/devicetree/bindings/display/verisilicon,dc.yaml +++ b/Documentation/devicetree/bindings/display/verisilicon,dc.yaml @@ -17,6 +17,7 @@ properties: items: - enum: - thead,th1520-dc8200 + - nuvoton,ma35d1-dcu - const: verisilicon,dc # DC IPs have discoverable ID/revision registers reg: @@ -77,6 +78,62 @@ required: - clock-names - ports +allOf: + - if: + properties: + compatible: + contains: + const: thead,th1520-dc8200 + then: + properties: + clocks: + minItems: 5 + maxItems: 5 + + clock-names: + minItems: 5 + maxItems: 5 + + resets: + minItems: 3 + maxItems: 3 + + reset-names: + minItems: 3 + maxItems: 3 + + required: + - resets + - reset-names + + - if: + properties: + compatible: + contains: + const: nuvoton,ma35d1-dcu + then: + properties: + clocks: + minItems: 2 + maxItems: 2 + + clock-names: + items: + - const: core + - const: pix0 + + resets: + minItems: 1 + maxItems: 1 + + reset-names: + items: + - const: core + + required: + - resets + - reset-names + additionalProperties: false examples: -- 2.43.0
