> -----Original Message-----
> From: Intel-gfx <[email protected]> On Behalf Of Sean
> Paul
> Sent: Friday, May 29, 2026 4:38 AM
> To: [email protected]; [email protected]; Borah,
> Chaitanya
> Kumar <[email protected]>
> Cc: Sean Paul <[email protected]>; Vivi, Rodrigo <[email protected]>;
> Joonas Lahtinen <[email protected]>; Tvrtko Ursulin
> <[email protected]>; David Airlie <[email protected]>; Simona Vetter
> <[email protected]>; [email protected]; dri-
> [email protected]
> Subject: [PATCH v3 1/2] drm/i915/color: Fix step discontinuity in Post-CSC
> Gamma LUT
>
> From: Sean Paul <[email protected]>
>
> Fix a step discontinuity in the Post-CSC Gamma LUT when SDR dimming is
> active by clamping Segment 2 to the last user-provided LUT entry value
> instead of
> hardcoding it to 1.0 (1 << 24).
>
Hi Sean,
Yeah it was done as UAPI was limited to 0.16 format and hence 1.0 value was
Not possible through UAPI. Expectation was that userspace will send LUTs in
range
Of 0 to 1.0 but agree it can limit the end point, so we can go with the
whatever highest
value userspace provides. We are planning a new LUT type to represent segmented
LUTS,
We can make this better including precision reporting and LUT caps.
But till then, ok to go with your change.
Reviewed-by: Uma Shankar <[email protected]>
> Signed-off-by: Sean Paul <[email protected]>
> Link: https://lore.kernel.org/intel-gfx/20260521180143.2143262-1-
> [email protected]/ #v1
> Link: https://lore.kernel.org/intel-gfx/20260525135730.1122696-1-
> [email protected]/ #v2
>
> Changes in v2:
> - Split out into separate patches for pre/post csc fixes
> - Dropped loop bounds fix in favor of [1] Changes in v3:
> - None
>
> [1]- https://lore.kernel.org/r/[email protected]
> ---
> drivers/gpu/drm/i915/display/intel_color.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c
> b/drivers/gpu/drm/i915/display/intel_color.c
> index 7ef870cd9a16..7185f3628dcf 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -4038,11 +4038,11 @@ xelpd_program_plane_post_csc_lut(struct intel_dsb
> *dsb,
> lut_val);
> }
>
> - /* Segment 2 */
> + /* Segment 2 - clamp to the last LUT value to prevent
> step
> +discontinuity */
> do {
> intel_de_write_dsb(display, dsb,
>
> PLANE_POST_CSC_GAMC_DATA_ENH(pipe, plane, 0),
> - (1 << 24));
> + lut_val);
> } while (i++ < 34);
> } else {
> /*TODO: Add for segment 0 */
> --
> Sean Paul, Software Engineer, Google / Chromium OS
