From: Midgy BALON <[email protected]> Add the RKNN core 0 and its IOMMU to the RK3568 SoC dtsi, mirroring the RK3588 pattern in rk3588-base.dtsi but with rk3568-specific clocks, resets, power domain, and a rockchip,pmu phandle required for the NPU NOC bus de-idle sequence.
Both nodes remain disabled by default; boards enable them as needed. Signed-off-by: Midgy BALON <[email protected]> --- arch/arm64/boot/dts/rockchip/rk356x-base.dtsi | 31 +++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi index 8893b7b6c..2c2a57ea3 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi @@ -929,6 +929,37 @@ qos_rga_wr: qos@fe158300 { reg = <0x0 0xfe158300 0x0 0x20>; }; + rknn_core_0: npu@fde40000 { + compatible = "rockchip,rk3568-rknn-core"; + reg = <0x0 0xfde40000 0x0 0x1000>, + <0x0 0xfde41000 0x0 0x1000>, + <0x0 0xfde43000 0x0 0x1000>; + reg-names = "pc", "cna", "core"; + interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru ACLK_NPU>, <&cru HCLK_NPU>, + <&scmi_clk SCMI_CLK_NPU>, <&cru PCLK_NPU_PRE>; + clock-names = "aclk", "hclk", "npu", "pclk"; + assigned-clocks = <&scmi_clk SCMI_CLK_NPU>; + assigned-clock-rates = <200000000>; + resets = <&cru SRST_A_NPU>, <&cru SRST_H_NPU>; + reset-names = "srst_a", "srst_h"; + power-domains = <&power RK3568_PD_NPU>; + rockchip,pmu = <&pmu>; + iommus = <&rknn_mmu_0>; + status = "disabled"; + }; + + rknn_mmu_0: iommu@fde4b000 { + compatible = "rockchip,iommu"; + reg = <0x0 0xfde4b000 0x0 0x40>; + interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "aclk", "iface"; + clocks = <&cru ACLK_NPU>, <&cru HCLK_NPU>; + power-domains = <&power RK3568_PD_NPU>; + #iommu-cells = <0>; + status = "disabled"; + }; + qos_npu: qos@fe180000 { compatible = "rockchip,rk3568-qos", "syscon"; reg = <0x0 0xfe180000 0x0 0x20>; -- 2.39.5
