Hi Biju, Thank you for the review.
On Wed, May 20, 2026 at 6:36 AM Biju Das <[email protected]> wrote: > > Hi Prabhakar, > > Thanks for the patch. > > > -----Original Message----- > > From: Prabhakar <[email protected]> > > Sent: 19 May 2026 17:08 > > Subject: [PATCH v4 4/5] drm: renesas: rz-du: Move mode_valid logic to > > per-SoC clock limits > > > > From: Lad Prabhakar <[email protected]> > > > > Move pixel clock validation from a fixed encoder check to per SoC > > constraints stored in > > rzg2l_du_device_info. > > > > Pixel clock limits differ across SoCs in the RZ DU family and cannot be > > expressed by a single shared > > rule. For example, RZ/G2UL and RZ/G2L limit the DPAD0 pixel clock to a > > narrow window, while other SoCs > > such as RZ/T2H require a wider operating range. > > > > Add mode_clock_min and mode_clock_max fields to rzg2l_du_device_info to > > describe the supported pixel > > clock range for each SoC. Update > > rzg2l_du_encoder_mode_valid() to check these bounds when evaluating > > DPAD0 outputs, returning MODE_CLOCK_LOW when the pixel clock falls below > > mode_clock_min and > > MODE_CLOCK_HIGH when it exceeds mode_clock_max. > > > > Populate the pixel clock limits for both the RZ/G2UL (R9A07G043U) and > > RZ/G2L (R9A07G044) variants to a > > minimum of 20875 kHz and a maximum of > > 83500 kHz. > > > > Signed-off-by: Lad Prabhakar <[email protected]> > > --- > > v3->v4: > > - Dropped per pad limits > > - Updated commit message to reflect the change in approach. > > > > v2->v3: > > - Moved clock limits from device_info to output_routing to allow > > per-output constraints. > > - Updated commit message to reflect the change in approach. > > > > v1->v2: > > - Dropped storing info pointer in struct rzg2l_du_encoder as it's not > > needed. > > --- > > drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c | 6 +++++- > > drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h | 4 ++++ > > drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.c | 9 ++++++++- > > 3 files changed, 17 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c > > b/drivers/gpu/drm/renesas/rz- > > du/rzg2l_du_drv.c > > index 0fef33a5a089..1e4b9f38c55b 100644 > > --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c > > +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c > > @@ -35,6 +35,8 @@ static const struct rzg2l_du_device_info > > rzg2l_du_r9a07g043u_info = { > > .port = 0, > > }, > > }, > > + .mode_clock_min = 20875, > > + .mode_clock_max = 83500, > > }; > > > > static const struct rzg2l_du_device_info rzg2l_du_r9a07g044_info = { @@ > > -48,7 +50,9 @@ static const > > struct rzg2l_du_device_info rzg2l_du_r9a07g044_info = { > > .possible_outputs = BIT(0), > > .port = 1, > > } > > - } > > + }, > > + .mode_clock_min = 20875, > > + .mode_clock_max = 83500, > > }; > > > > static const struct rzg2l_du_device_info rzg2l_du_r9a09g057_info = { diff > > --git > > a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h > > b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h > > index 58806c2a8f2b..885558eb9547 100644 > > --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h > > +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h > > @@ -44,10 +44,14 @@ struct rzg2l_du_output_routing { > > * struct rzg2l_du_device_info - DU model-specific information > > * @channels_mask: bit mask of available DU channels > > * @routes: array of CRTC to output routes, indexed by output > > (RZG2L_DU_OUTPUT_*) > > + * @mode_clock_min: minimum pixel clock in kHz > > + * @mode_clock_max: maximum pixel clock in kHz > > */ > > struct rzg2l_du_device_info { > > unsigned int channels_mask; > > struct rzg2l_du_output_routing routes[RZG2L_DU_OUTPUT_MAX]; > > + u32 mode_clock_min; > > + u32 mode_clock_max; > > }; > > > > #define RZG2L_DU_MAX_CRTCS 1 > > diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.c > > b/drivers/gpu/drm/renesas/rz- > > du/rzg2l_du_encoder.c > > index 0e567b57a408..56220139a149 100644 > > --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.c > > +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.c > > @@ -50,8 +50,15 @@ rzg2l_du_encoder_mode_valid(struct drm_encoder *encoder, > > const struct drm_display_mode *mode) { > > struct rzg2l_du_encoder *renc = to_rzg2l_encoder(encoder); > > + struct rzg2l_du_device *rcdu = to_rzg2l_du_device(renc->base.dev); > > + const struct rzg2l_du_device_info *info = rcdu->info; > > > > - if (renc->output == RZG2L_DU_OUTPUT_DPAD0 && mode->clock > 83500) > > + if (renc->output != RZG2L_DU_OUTPUT_DPAD0) > > + return MODE_OK; > > + > > + if (info->mode_clock_min && mode->clock < info->mode_clock_min) > > I will avoid checking the first part as it is mandatory for SoCs with DPI > support > and DPI check above make sure that this part of the code is reachable only > for DPI > output. > Will you fix up while applying or shall I send a new version? Cheers, Prabhakar > > + return MODE_CLOCK_LOW; > > + if (info->mode_clock_max && mode->clock > info->mode_clock_max) > > Same here. > > Cheers, > Biju > > > return MODE_CLOCK_HIGH; > > > > return MODE_OK; > > -- > > 2.54.0 >
