This 720x1600 panel is found in several Motorola/Lenovo smartphones like
the Moto G9 Play (guamp). The initialization sequence is based on the
datasheet. Add it to the existing HX83102 panel driver.
Signed-off-by: Val Packett <[email protected]>
---
drivers/gpu/drm/panel/panel-himax-hx83102.c | 86 +++++++++++++++++++++
1 file changed, 86 insertions(+)
diff --git a/drivers/gpu/drm/panel/panel-himax-hx83102.c
b/drivers/gpu/drm/panel/panel-himax-hx83102.c
index 1d3bb5dca559..34e0e956db48 100644
--- a/drivers/gpu/drm/panel/panel-himax-hx83102.c
+++ b/drivers/gpu/drm/panel/panel-himax-hx83102.c
@@ -701,6 +701,67 @@ static int starry_2082109qfh040022_50e_init(struct hx83102
*ctx)
return dsi_ctx.accum_err;
}
+static int holitech_htf065h045_init(struct hx83102 *ctx)
+{
+ struct mipi_dsi_multi_context dsi_ctx = { .dsi = ctx->dsi };
+
+ msleep(50);
+
+ hx83102_enable_extended_cmds(&dsi_ctx, true);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPOWER, 0x22, 0x44,
0x27, 0x27, 0x32,
+ 0x52, 0x57, 0x39, 0x08, 0x08, 0x08);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETDISP, 0x00, 0x00,
0x06, 0x40, 0x00,
+ 0x0e, 0xae, 0x38, 0x00, 0x00, 0x00, 0x00,
0xf4, 0xa0);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCYC, 0x01, 0x58,
0x01, 0x58, 0x01,
+ 0x58, 0x03, 0x58, 0x03, 0xff, 0x01, 0x20,
0x00, 0xff);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPANEL, 0x02);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP0, 0x00, 0x00,
0x00, 0x00, 0x00,
+ 0x10, 0x00, 0x17, 0x00, 0x63, 0x37, 0x0e,
0x0e, 0x00, 0x00,
+ 0x32, 0x10, 0x08, 0x00, 0x08, 0x32, 0x16,
0x4e, 0x06, 0x4e);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPWM, 0x04, 0x0c,
0xb2, 0x01);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP1, 0x24, 0x25,
0x18, 0x18, 0x19,
+ 0x19, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
0x18, 0x18, 0x18,
+ 0x18, 0x18, 0x18, 0x06, 0x07, 0x04, 0x05,
0x18, 0x18, 0x18,
+ 0x18, 0x02, 0x03, 0x00, 0x01, 0x20, 0x21,
0x18, 0x18, 0x18,
+ 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
0x18, 0x18);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP2, 0x00, 0x09,
0x16, 0x1f, 0x28,
+ 0x4b, 0x65, 0x6d, 0x74, 0x70, 0x89, 0x8d,
0x91, 0xa0, 0x9e,
+ 0xa8, 0xb2, 0xc8, 0xc9, 0x65, 0x6d, 0x78,
0x7f, 0x00, 0x09,
+ 0x16, 0x1f, 0x28, 0x4b, 0x65, 0x6d, 0x74,
0x70, 0x89, 0x8d,
+ 0x91, 0xa0, 0x9e, 0xa8, 0xb2, 0xc8, 0xc9,
0x65, 0x6d, 0x78,
+ 0x7f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTP1, 0xff, 0x14,
0x00, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x01);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTP1, 0x01);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x02);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3, 0xff, 0xff,
0xff, 0xff, 0xff,
+ 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf0);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x03);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3, 0xaa, 0xaa,
0xaa, 0xaa, 0xaa,
+ 0xa0, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa0,
0xaa, 0xaa, 0xaa,
+ 0xaa, 0xaa, 0xa0, 0xaa, 0xaa, 0xaa, 0xaa,
0xaa, 0xa0);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETMIPI, 0x70, 0x23,
0xa8, 0x93, 0xb2,
+ 0xc0, 0xc0, 0x01, 0x10, 0x00, 0x00, 0x00,
0x0d, 0x3d, 0x82,
+ 0x77, 0x04, 0x01, 0x04);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x01);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCLOCK, 0x01);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCLOCK, 0x00, 0x53,
0x00, 0x02, 0x59);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPTBA, 0xfc, 0x00,
0x04, 0x9e, 0xf6,
+ 0x00, 0x5d);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x02);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCYC, 0x42, 0x00,
0x33, 0x00, 0x33,
+ 0x88, 0xb3, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPCTRL, 0x20, 0x01);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x02);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPOWER, 0x7f, 0x03,
0xf5);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x00);
+
+ return dsi_ctx.accum_err;
+}
+
static const struct drm_display_mode starry_mode = {
.clock = 162680,
.hdisplay = 1200,
@@ -833,6 +894,28 @@ static const struct hx83102_panel_desc
starry_2082109qfh040022_50e_desc = {
.init = starry_2082109qfh040022_50e_init,
};
+static const struct drm_display_mode holitech_htf065h045_default_mode = {
+ .clock = 90720,
+ .hdisplay = 720,
+ .hsync_start = 720 + 40,
+ .hsync_end = 720 + 40 + 40,
+ .htotal = 720 + 40 + 40 + 40,
+ .vdisplay = 1600,
+ .vsync_start = 1600 + 186,
+ .vsync_end = 1600 + 186 + 2,
+ .vtotal = 1600 + 186 + 2 + 12,
+ .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
+};
+
+static const struct hx83102_panel_desc holitech_htf065h045_desc = {
+ .modes = &holitech_htf065h045_default_mode,
+ .size = {
+ .width_mm = 68,
+ .height_mm = 151,
+ },
+ .init = holitech_htf065h045_init,
+};
+
static int hx83102_enable(struct drm_panel *panel)
{
msleep(130);
@@ -1069,6 +1152,9 @@ static const struct of_device_id hx83102_of_match[] = {
{ .compatible = "starry,himax83102-j02",
.data = &starry_desc
},
+ { .compatible = "holitech,htf065h045",
+ .data = &holitech_htf065h045_desc
+ },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, hx83102_of_match);
