From: Artem Lytkin <[email protected]> The L2_PWRTRANS_HI register offset was 0x204, but it should be 0x224. All other _LO/_HI register pairs in the file differ by 4 bytes, and the C Panthor driver defines L2_PWRTRANS at 0x220, making the correct _HI offset 0x224.
The register is currently unused, so this has no runtime impact yet. Signed-off-by: Artem Lytkin <[email protected]> --- drivers/gpu/drm/tyr/regs.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/tyr/regs.rs b/drivers/gpu/drm/tyr/regs.rs index b51e09fe2fc4..acc29f7950c1 100644 --- a/drivers/gpu/drm/tyr/regs.rs +++ b/drivers/gpu/drm/tyr/regs.rs @@ -81,7 +81,7 @@ pub(crate) fn write(&self, dev: &Device<Bound>, iomem: &Devres<IoMem>, value: u3 pub(crate) const L2_PWRON_LO: Register<0x1a0> = Register; pub(crate) const L2_PWRON_HI: Register<0x1a4> = Register; pub(crate) const L2_PWRTRANS_LO: Register<0x220> = Register; -pub(crate) const L2_PWRTRANS_HI: Register<0x204> = Register; +pub(crate) const L2_PWRTRANS_HI: Register<0x224> = Register; pub(crate) const L2_PWRACTIVE_LO: Register<0x260> = Register; pub(crate) const L2_PWRACTIVE_HI: Register<0x264> = Register; -- 2.43.0
