On Thu, 15 Jan 2026 03:39:42 +0100, Marek Vasut wrote:
> Describe 1..4 DSI lanes as supported. Internally, this bridge is
> an ChipOne ICN6211 which loads its register configuration from a
> dedicated storage and its I2C does not seem to be accessible. The
> ICN6211 supports up to 4 DSI lanes, so this is a hard limit for
> this bridge. The lane configuration is preconfigured in the bridge
> for each of the WaveShare panels.
>
> [...]
Applied, thanks!
[1/2] dt-bindings: display: bridge: waveshare,dsi2dpi: Document 1..4 DSI lane
support
commit: 2befa6407d5c8b543be32c2276d396db395d9d02
[2/2] drm/bridge: waveshare-dsi: Add support for 1..4 DSI data lanes
commit: fca11428425e92bf21d4a7f5865708c5e64430e4
Best regards,
--
Luca Ceresoli <[email protected]>
