On Mon, Mar 02, 2026 at 02:03:44PM -0500, Hugo Villeneuve wrote: > From: Hugo Villeneuve <[email protected]> > > Move SD support to a separate include, since it cannot be used at the
s/include/dtsi/ > same time as the Wifi/BT module. what's relation ship between wifi/bt? you just move sd related part to a dtsi file. Frank > > Signed-off-by: Hugo Villeneuve <[email protected]> > --- > .../dts/nxp/imx/imx6ul-var-som-common.dtsi | 33 ++++++++++++ > .../imx/imx6ul-var-som-concerto-common.dtsi | 51 ------------------- > .../dts/nxp/imx/imx6ul-var-som-concerto.dts | 1 + > .../boot/dts/nxp/imx/imx6ul-var-som-sd.dtsi | 27 ++++++++++ > .../dts/nxp/imx/imx6ull-var-som-concerto.dts | 1 + > 5 files changed, 62 insertions(+), 51 deletions(-) > create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ul-var-som-sd.dtsi > > diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi > b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi > index 22b0c4e0725a5..dd4ecff1eb786 100644 > --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi > +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi > @@ -139,6 +139,39 @@ MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x1b0b1 > >; > }; > > + pinctrl_usdhc1: usdhc1grp { > + fsl,pins = < > + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 > + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x17059 > + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 > + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 > + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 > + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 > + >; > + }; > + > + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { > + fsl,pins = < > + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 > + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 > + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 > + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 > + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 > + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 > + >; > + }; > + > + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { > + fsl,pins = < > + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 > + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 > + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 > + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 > + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 > + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 > + >; > + }; > + > pinctrl_usdhc2: usdhc2grp { > fsl,pins = < > MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 > diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi > b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi > index 10a23ae104359..ea8d9905ce6e7 100644 > --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi > +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi > @@ -186,45 +186,6 @@ MX6UL_PAD_UART3_TX_DATA__ANATOP_OTG1_ID 0x17059 > >; > }; > > - pinctrl_usdhc1: usdhc1grp { > - fsl,pins = < > - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 > - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x17059 > - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 > - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 > - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 > - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 > - >; > - }; > - > - pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { > - fsl,pins = < > - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 > - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 > - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 > - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 > - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 > - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 > - >; > - }; > - > - pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { > - fsl,pins = < > - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 > - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 > - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 > - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 > - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 > - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 > - >; > - }; > - > - pinctrl_usdhc1_gpio: usdhc1-gpiogrp { > - fsl,pins = < > - MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0x1b0b1 /* CD */ > - >; > - }; > - > pinctrl_wdog: wdoggrp { > fsl,pins = < > MX6UL_PAD_GPIO1_IO01__WDOG1_WDOG_B 0x78b0 > @@ -286,18 +247,6 @@ &usbotg2 { > status = "okay"; > }; > > -&usdhc1 { > - pinctrl-names = "default", "state_100mhz", "state_200mhz"; > - pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>; > - pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>; > - pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>; > - cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; > - no-1-8-v; > - keep-power-in-suspend; > - wakeup-source; > - status = "okay"; > -}; > - > &wdog1 { > pinctrl-names = "default"; > pinctrl-0 = <&pinctrl_wdog>; > diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts > b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts > index 11b45f105b7ad..85ebac30d7bed 100644 > --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts > +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts > @@ -11,6 +11,7 @@ > > #include "imx6ul-var-som.dtsi" > #include "imx6ul-var-som-concerto-common.dtsi" > +#include "imx6ul-var-som-sd.dtsi" > > / { > model = "Variscite VAR-SOM-6UL Concerto Board (6UL CPU)"; > diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-sd.dtsi > b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-sd.dtsi > new file mode 100644 > index 0000000000000..0e6d9b945eb4a > --- /dev/null > +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-sd.dtsi > @@ -0,0 +1,27 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Support optional SD card interface on Variscite VAR-SOM-6UL module. > + * > + * Copyright 2019-2024 Variscite Ltd. > + * Copyright 2026 Dimonoff > + */ > + > +&iomuxc { > + pinctrl_usdhc1_gpio: usdhc1-gpiogrp { > + fsl,pins = < > + MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0x1b0b1 /* CD */ > + >; > + }; > +}; > + > +&usdhc1 { > + pinctrl-names = "default", "state_100mhz", "state_200mhz"; > + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>; > + pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>; > + pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>; > + cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; > + no-1-8-v; > + keep-power-in-suspend; > + wakeup-source; > + status = "okay"; > +}; > diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts > b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts > index 7c601af2657d7..ebf88c3e1addc 100644 > --- a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts > +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts > @@ -10,6 +10,7 @@ > > #include "imx6ull-var-som.dtsi" > #include "imx6ul-var-som-concerto-common.dtsi" > +#include "imx6ul-var-som-sd.dtsi" > > / { > model = "Variscite VAR-SOM-6UL Concerto Board (6ULL CPU)"; > -- > 2.47.3 >
