On Fri, Dec 5, 2025 at 2:53 PM Maxime Ripard <[email protected]> wrote:
> - We need to figure out the bridge ordering mess in the first place I was thinking about what we can do here, adding various flags was discussed and deemed too kludgy. What exists in the kernel are things such as the MMC power sequencer which can be found in drivers/mmc/core/pwrseq_simple.c drivers/mmc/core/pwrseq_emmc.c drivers/mmc/core/pwrseq_sd8787.c with some DT bindings in Documentation/devicetree/bindings/mmc/mmc-pwrseq-simple.yaml Documentation/devicetree/bindings/mmc/mmc-pwrseq-emmc.yaml Documentation/devicetree/bindings/mmc/mmc-pwrseq-sd8787.yaml So here the approach is that the specific sequencing requirements are added to the hardware description (the device tree) but there the resources are really flat, then the driver for each type of sequence takes care of the semantics, i.e. the actual sequencing and ordering. Maybe we want to look into something like this? Yours, Linus Walleij
