On Wed, Nov 26, 2025 at 10:31:30PM +0100, Anna Maniscalco wrote:
> Previously this register would become 0 after IFPC took place which
> broke all usages of counters.
>
> Fixes: a6a0157cc68e ("drm/msm/a6xx: Enable IFPC on Adreno X1-85")
> Signed-off-by: Anna Maniscalco <[email protected]>
> ---
> Changes in v2:
> - Added Fixes tag
Cc: [email protected]
Reviewed-by: Dmitry Baryshkov <[email protected]>
> - Link to v1:
> https://lore.kernel.org/r/[email protected]
> ---
> drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 1 +
> 1 file changed, 1 insertion(+)
>
--
With best wishes
Dmitry
