> > The "CXL" ranges that are remapped into BAR 2 and BAR 4 areas are not PCI > MMIO, they actually run over the CXL-like coherent interconnect and for > the purposes of DMA behave identically to DRAM. We don't try to model this > distinction between true PCI BAR memory that takes a real PCI path and the > "CXL" memory that takes a different path in the p2p framework for now. > > Signed-off-by: Jason Gunthorpe <[email protected]> > Reviewed-by: Kevin Tian <[email protected]> > Tested-by: Alex Mastro <[email protected]> > Tested-by: Nicolin Chen <[email protected]> > Signed-off-by: Leon Romanovsky <[email protected]> > ---
Reviewed-by: Ankit Agrawal <[email protected]>
