Dear Kuba, Thanks for your efforts.
On 11/16/25 2:47 PM, Kuba Szczodrzyński wrote: > Some Allwinner chips (notably the D1s/T113 and the A100) have a "combo > MIPI DSI D-PHY" which is required when using single-link LVDS0. > > In this mode, the DSI peripheral is not used and the PHY is not > configured for DSI. Instead, the COMBO_PHY_REGx registers are set to > enable LVDS operation. > > Enable the PHY driver to work in LVDS mode on chips with a combo D-PHY. > > Also change the SUN50I_COMBO_PHY_REG1 macro names to reflect the correct > register name. > > Signed-off-by: Kuba Szczodrzyński <[email protected]> > --- > drivers/phy/allwinner/phy-sun6i-mipi-dphy.c | 70 ++++++++++++++++++++- > 1 file changed, 68 insertions(+), 2 deletions(-) I tried integrating your changes in A133 display pipeline and I couldn't get the LVDS working. Am still narrowing down what is missing in your patch. Driver registration is success and I can see /dev/fb0 as well. But nothing on the display itself. But with below changes from my patch, diff --git a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c index 36eab95271b2..d164b2ea5dfd 100644 --- a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c +++ b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c @@ -314,13 +314,11 @@ static void sun50i_a100_mipi_dphy_tx_power_on(struct sun6i_dphy *dphy) /* Disable sigma-delta modulation. */ regmap_write(dphy->regs, SUN50I_DPHY_PLL_REG2, 0); - regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA4_REG, - SUN6I_DPHY_ANA4_REG_EN_MIPI, - SUN6I_DPHY_ANA4_REG_EN_MIPI); - regmap_update_bits(dphy->regs, SUN50I_COMBO_PHY_REG0, + SUN50I_COMBO_PHY_REG0_EN_LVDS | SUN50I_COMBO_PHY_REG0_EN_MIPI | SUN50I_COMBO_PHY_REG0_EN_COMBOLDO, + SUN50I_COMBO_PHY_REG0_EN_LVDS | SUN50I_COMBO_PHY_REG0_EN_MIPI | SUN50I_COMBO_PHY_REG0_EN_COMBOLDO); @@ -528,6 +526,22 @@ static int sun6i_dphy_exit(struct phy *phy) return 0; } LVDS works fine. Could you please share the diff of your dts / dtsi? Thanks, Parthiban
