From: Derek Foreman <[email protected]>

Register the color format property in the dw_hdmi_qp-rockchip driver,
and act on requested format changes as part of the connector state in
the vop2 video output driver.

Signed-off-by: Derek Foreman <[email protected]>
Signed-off-by: Marius Vlad <[email protected]>
Signed-off-by: Nicolas Frattaroli <[email protected]>
---
 drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c |  3 ++
 drivers/gpu/drm/rockchip/rockchip_drm_vop2.c   | 46 ++++++++++++++++++++++++++
 drivers/gpu/drm/rockchip/rockchip_drm_vop2.h   |  2 ++
 3 files changed, 51 insertions(+)

diff --git a/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c 
b/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c
index 7c294751de19..7028166fdace 100644
--- a/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c
@@ -635,6 +635,9 @@ static int dw_hdmi_qp_rockchip_bind(struct device *dev, 
struct device *master,
                return dev_err_probe(hdmi->dev, PTR_ERR(connector),
                                     "Failed to init bridge connector\n");
 
+       if (!drm_mode_create_hdmi_color_format_property(connector, 
supported_colorformats))
+               drm_connector_attach_color_format_property(connector);
+
        return drm_connector_attach_encoder(connector, encoder);
 }
 
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c 
b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
index 498df0ce4680..2fc9b21c5522 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
@@ -1549,6 +1549,50 @@ static void vop2_dither_setup(struct drm_crtc *crtc, u32 
*dsp_ctrl)
                                DITHER_DOWN_ALLEGRO);
 }
 
+static void vop2_bcsh_config(struct drm_crtc *crtc, struct vop2_video_port *vp)
+{
+       struct drm_connector_list_iter conn_iter;
+       struct drm_connector *connector;
+       u32 format = 0;
+       enum drm_colorspace colorspace = 0;
+       u32 val = 0;
+
+       drm_connector_list_iter_begin(crtc->dev, &conn_iter);
+       drm_for_each_connector_iter(connector, &conn_iter) {
+               if (!(crtc->state->connector_mask & 
drm_connector_mask(connector)))
+                       continue;
+
+               format = connector->state->color_format;
+               colorspace = connector->state->colorspace;
+               break;
+       }
+       drm_connector_list_iter_end(&conn_iter);
+
+       if (format == DRM_COLOR_FORMAT_YCBCR420 ||
+           format == DRM_COLOR_FORMAT_YCBCR444 ||
+           format == DRM_COLOR_FORMAT_YCBCR422) {
+               val = RK3568_VP_BCSH_CTRL__BCSH_R2Y_EN | BIT(7);
+
+               switch (colorspace) {
+               case DRM_MODE_COLORIMETRY_BT2020_RGB:
+               case DRM_MODE_COLORIMETRY_BT2020_YCC:
+                       val |= BIT(7) | BIT(6);
+                       break;
+               case DRM_MODE_COLORIMETRY_BT709_YCC:
+                       val |= BIT(6);
+                       break;
+               default:
+                       break;
+               }
+               if (colorspace == DRM_MODE_COLORIMETRY_BT2020_RGB ||
+                   colorspace == DRM_MODE_COLORIMETRY_BT2020_YCC)
+                       val |= BIT(6);
+       }
+
+       vop2_vp_write(vp, RK3568_VP_BCSH_CTRL, val);
+       vop2_vp_write(vp, RK3568_VP_BCSH_COLOR_BAR, 0);
+}
+
 static void vop2_post_config(struct drm_crtc *crtc)
 {
        struct vop2_video_port *vp = to_vop2_video_port(crtc);
@@ -1600,6 +1644,8 @@ static void vop2_post_config(struct drm_crtc *crtc)
        }
 
        vop2_vp_write(vp, RK3568_VP_DSP_BG, 0);
+
+       vop2_bcsh_config(crtc, vp);
 }
 
 static int us_to_vertical_line(struct drm_display_mode *mode, int us)
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h 
b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h
index 9124191899ba..33fdc9d8d819 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h
@@ -637,6 +637,8 @@ enum dst_factor_mode {
 
 #define RK3568_REG_CFG_DONE__GLB_CFG_DONE_EN           BIT(15)
 
+#define RK3568_VP_BCSH_CTRL__BCSH_R2Y_EN               BIT(4)
+
 #define RK3568_VP_DSP_CTRL__STANDBY                    BIT(31)
 #define RK3568_VP_DSP_CTRL__DSP_LUT_EN                 BIT(28)
 #define RK3568_VP_DSP_CTRL__DITHER_DOWN_MODE           BIT(20)

-- 
2.51.2

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