Add support for auxless waketime calculation for DP2.1 ALPM
as dependent parameter got changed.

v1: Initial version.
v2: Use intel_dp_is_uhbr(). [Jani]

Cc: Jouni Högander <[email protected]>
Signed-off-by: Animesh Manna <[email protected]>
---
 drivers/gpu/drm/i915/display/intel_alpm.c | 63 +++++++++++++++++++----
 1 file changed, 53 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c 
b/drivers/gpu/drm/i915/display/intel_alpm.c
index b4b874dd3725..81472254ab73 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -100,23 +100,64 @@ static int get_lfps_half_cycle_clocks(const struct 
intel_crtc_state *crtc_state)
 
 static int get_tphy2_p2_to_p0(const struct intel_crtc_state *crtc_state)
 {
-       return 12 * 1000;
+       struct intel_display *display = to_intel_display(crtc_state);
+
+       return DISPLAY_VER(display) >= 35 ? (40 * 1000) : (12 * 1000);
 }
 
-static int get_establishment_period(const struct intel_crtc_state *crtc_state)
+static int get_establishment_period(struct intel_dp *intel_dp,
+                                   const struct intel_crtc_state *crtc_state)
 {
        int t1 = 50 * 1000;
-       int tps4 = 252;
+       int tps4 = intel_dp_is_uhbr(crtc_state) ? (396 * 32) : (252 * 10);
        /* port_clock is link rate in 10kbit/s units */
-       int tml_phy_lock = 1000 * 1000 * tps4 / crtc_state->port_clock;
+       int tml_phy_lock = 1000 * 1000 * tps4 / crtc_state->port_clock / 10;
+       int lttpr_count = 0;
        int tcds, establishment_period;
 
-       tcds = (7 + DIV_ROUND_UP(6500, tml_phy_lock) + 1) * tml_phy_lock;
-       establishment_period = (SILENCE_PERIOD_TIME + t1 + tcds);
+       if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {
+               tcds = (7 + DIV_ROUND_UP(6500, tml_phy_lock) + 1) * 
tml_phy_lock;
+       } else {
+               tcds = 7 * tml_phy_lock;
+               lttpr_count = drm_dp_lttpr_count(intel_dp->lttpr_common_caps);
+       }
+
+       if (lttpr_count) {
+               int tlw = 13000;
+               int tcs = 10000;
+               int tlfps_period = get_lfps_cycle_time(crtc_state);
+               int tdcs = (SILENCE_PERIOD_TIME + t1 + tcs +
+                           (lttpr_count - 1) * (tlw + tlfps_period));
+               int tacds = 70000;
+               int tds = (lttpr_count - 1) * 7 * tml_phy_lock;
+
+               /* tdrl is same as tcds*/
+               establishment_period = tlw + tlfps_period + tdcs + tacds + tds 
+ tcds;
+       } else {
+               /* TODO: Add a check for data realign by DPCD 0x116[3] */
+
+               establishment_period = (SILENCE_PERIOD_TIME + t1 + tcds);
+       }
 
        return establishment_period;
 }
 
+static int get_switch_to_active(const struct intel_crtc_state *crtc_state)
+{
+       int port_clock = crtc_state->port_clock;
+       int switch_to_active;
+
+       if (intel_dp_is_uhbr(crtc_state)) {
+               int symbol_clock = port_clock / 
intel_dp_link_symbol_size(port_clock);
+
+               switch_to_active = 32 * DIV_ROUND_UP((396 + 3 + 64), 
symbol_clock);
+       } else {
+               switch_to_active = 0;
+       }
+
+       return switch_to_active;
+}
+
 /*
  * AUX-Less Wake Time = CEILING( ((PHY P2 to P0) + tLFPS_Period, Max+
  * tSilence, Max+ tPHY Establishment + tCDS) / tline)
@@ -136,13 +177,15 @@ static int get_establishment_period(const struct 
intel_crtc_state *crtc_state)
  * tML_PHY_LOCK = TPS4 Length * ( 10 / (Link Rate in MHz) )
  * TPS4 Length = 252 Symbols
  */
-static int _lnl_compute_aux_less_wake_time(const struct intel_crtc_state 
*crtc_state)
+static int _lnl_compute_aux_less_wake_time(struct intel_dp *intel_dp,
+                                          const struct intel_crtc_state 
*crtc_state)
 {
        int tphy2_p2_to_p0 = get_tphy2_p2_to_p0(crtc_state);
-       int establishment_period = get_establishment_period(crtc_state);
+       int establishment_period = get_establishment_period(intel_dp, 
crtc_state);
+       int switch_to_active = get_switch_to_active(crtc_state);
 
        return DIV_ROUND_UP(tphy2_p2_to_p0 + get_lfps_cycle_time(crtc_state) +
-                           establishment_period, 1000);
+                           establishment_period + switch_to_active, 1000);
 }
 
 static int
@@ -154,7 +197,7 @@ _lnl_compute_aux_less_alpm_params(struct intel_dp *intel_dp,
                lfps_half_cycle;
 
        aux_less_wake_time =
-               _lnl_compute_aux_less_wake_time(crtc_state);
+               _lnl_compute_aux_less_wake_time(intel_dp, crtc_state);
        aux_less_wake_lines = 
intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode,
                                                       aux_less_wake_time);
        silence_period = get_silence_period_symbols(crtc_state);
-- 
2.29.0

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