On Wed, 2025-11-12 at 13:23 +0000, Tvrtko Ursulin wrote: > > Hi, > > On 12/11/2025 12:31, Chenna Kesava Raju (QUIC) wrote: > > Hi All, > > > > We are currently developing a driver using the Accel framework to > > enable > > applications to offload their tasks to the NPU. > > > > As part of this effort, we are considering the use of the DRM > > scheduler > > for job management. These applications may have their own priority > > levels to manage task execution efficiently on the NPU. However, > > since > > the DRM scheduler currently supports only a limited set of job > > priority > > levels (DRM_SCHED_PRIORITY_KERNEL, DRM_SCHED_PRIORITY_HIGH, > > DRM_SCHED_PRIORITY_NORMAL, and DRM_SCHED_PRIORITY_LOW), we have a > > couple > > of questions:
Note that many users (Nouveau, Xe, …) by now always use drm_sched with a 1:1 relationship between sched_entity and sched itself. So there isn't real scheduling anymore for many users and priority levels become pointless. With the industry apparently moving to firmware scheduling, I suppose that big interest in features like more priority levels is little (though not non-existent. See Tvrtko's link). So I guess the most interesting question is what the ringbuffer layout on your chip looks like. Nr of rings, way of creating them etc. P.
