On 11/10/25 5:37 PM, Akhil P Oommen wrote:
> As per the recommendation, A7x and newer GPUs should flush the LRZ cache
> before switching the pagetable. Update a6xx_set_pagetable() to do this.
> While we are at it, sync both BV and BR before issuing a
> CP_RESET_CONTEXT_STATE command, to match the downstream sequence.
>
> Fixes: af66706accdf ("drm/msm/a6xx: Add skeleton A7xx support")
> Signed-off-by: Akhil P Oommen <[email protected]>
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 10 ++++++++--
> 1 file changed, 8 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> index b8f8ae940b55..6f7ed07670b1 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> @@ -224,7 +224,7 @@ static void a6xx_set_pagetable(struct a6xx_gpu *a6xx_gpu,
> OUT_RING(ring, submit->seqno - 1);
>
> OUT_PKT7(ring, CP_THREAD_CONTROL, 1);
> - OUT_RING(ring, CP_SET_THREAD_BOTH);
> + OUT_RING(ring, CP_THREAD_CONTROL_0_SYNC_THREADS |
> CP_SET_THREAD_BOTH);
>
> /* Reset state used to synchronize BR and BV */
> OUT_PKT7(ring, CP_RESET_CONTEXT_STATE, 1);
> @@ -235,7 +235,13 @@ static void a6xx_set_pagetable(struct a6xx_gpu *a6xx_gpu,
> CP_RESET_CONTEXT_STATE_0_RESET_GLOBAL_LOCAL_TS);
>
> OUT_PKT7(ring, CP_THREAD_CONTROL, 1);
> - OUT_RING(ring, CP_SET_THREAD_BR);
> + OUT_RING(ring, CP_THREAD_CONTROL_0_SYNC_THREADS |
> CP_SET_THREAD_BOTH);
IIUC downstream doesn't sync here since there's a sync after the LRZ
flush, but I don't think that's a meaningful difference.
Reviewed-by: Konrad Dybcio <[email protected]>
Konrad
