From: Joel Fernandes <[email protected]> Add definition for RISCV_CPUCTL register and use it in a new falcon API to check if the RISC-V core of a Falcon is active. It is required by the sequencer to know if the GSP's RISCV processor is active.
Reviewed-by: Lyude Paul <[email protected]> Signed-off-by: Joel Fernandes <[email protected]> Signed-off-by: Alexandre Courbot <[email protected]> --- drivers/gpu/nova-core/falcon.rs | 9 +++++++++ drivers/gpu/nova-core/regs.rs | 7 ++++++- 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/nova-core/falcon.rs b/drivers/gpu/nova-core/falcon.rs index fe5b3256d972..4c1f36073533 100644 --- a/drivers/gpu/nova-core/falcon.rs +++ b/drivers/gpu/nova-core/falcon.rs @@ -612,4 +612,13 @@ pub(crate) fn signature_reg_fuse_version( self.hal .signature_reg_fuse_version(self, bar, engine_id_mask, ucode_id) } + + /// Check if the RISC-V core is active. + /// + /// Returns `true` if the RISC-V core is active, `false` otherwise. + #[expect(unused)] + pub(crate) fn is_riscv_active(&self, bar: &Bar0) -> bool { + let cpuctl = regs::NV_PRISCV_RISCV_CPUCTL::read(bar, &E::ID); + cpuctl.active_stat() + } } diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs index 41fdda8a0748..5d5ba766cd61 100644 --- a/drivers/gpu/nova-core/regs.rs +++ b/drivers/gpu/nova-core/regs.rs @@ -339,7 +339,12 @@ pub(crate) fn mem_scrubbing_done(self) -> bool { // PRISCV -register!(NV_PRISCV_RISCV_BCR_CTRL @ PFalconBase[0x00001668] { +register!(NV_PRISCV_RISCV_CPUCTL @ PFalcon2Base[0x00000388] { + 0:0 halted as bool; + 7:7 active_stat as bool; +}); + +register!(NV_PRISCV_RISCV_BCR_CTRL @ PFalcon2Base[0x00000668] { 0:0 valid as bool; 4:4 core_select as bool => PeregrineCoreSelect; 8:8 br_fetch as bool; -- 2.51.2
