On Wed, 5 Nov 2025 17:25:29 -0500 Chris Brandt <[email protected]> wrote:
> Convert the limited MIPI clock calculations to a full range of settings > based on math including H/W limitation validation. > Since the required DSI division setting must be specified from external > sources before calculations, expose a new API to set it. > > Signed-off-by: Chris Brandt <[email protected]> > Reviewed-by: Biju Das <[email protected]> > Tested-by: Biju Das <[email protected]> > > --- > v1->v2: > - Remove unnecessary parentheses > - Add target argument to new API > - DPI mode has more restrictions on DIV_A and DIV_B > > v2->v3: > - Removed Empty lines (Hugo) > - Add dummy for compile-testing CONFIG_CLK_RZG2L=n case (Geert) > - Renamed label found_dsi_div to calc_pll_clk (Hugo) > - Renamed label found_clk to clk_valid (Hugo) > - Removed 'found' var because not needed > - Move 'foutpostdiv_rate =' after if(foutvco_rate > 1500000000) (Hugo) > - Move PLL5_TARGET_* for new API to renesas.h (Hugo,Geert) > - Convert #define macros PLL5_TARGET_* to enum (Geert) > - static {unsigned} int dsi_div_ab; (Geert) > - {unsigned} int a, b; (Geert) > - Change "((1 << a) * (b + 1))" to "(b + 1) << a" (Geert) > - Change "foutvco_rate = rate * (1 << xxx ) * ..." to " = rate * ... * << xxx > (Geert) > - Move (u64) outside of modulo operation to avoid helper on 32-bit compiles > (Geert) > - Change DIV_ROUND_CLOSEST_ULL() to DIV_ROUND_CLOSEST() (Geert) > - void rzg2l_cpg_dsi_div_set_divider({unsinged} int divider, int target) > - Change "dsi_div_ab = (1 << AAA) * (BBB + 1)" to " = (BBB + 1) << AAA (Geert) > - Added Reviewed-by and Tested-by (Biju) > > v3->v4: > - Changed <,> to <=,>= (Hugo) > - Removed duplicate code bock (copy/paste mistake) (Hugo) > - Fix dummy for rzg2l_cpg_dsi_div_set_divider when CONFIG_CLK_RZG2L=n (Geert) > - Remove comment "Below conditions must be set.." (Hugo) > - Remove +1,-1 from pl5_intin comparison math (kernel test robot) > - Remove default register settings (PLL5_xxx_DEF) because makes no sense > - If any calcualtion error, print a message and return a rate of 0 > - Rename global var "dsi_div_ab" to "dsi_div_ab_desired" > - Check the range of hsclk > - The correct clock parent is determined by if the divider is even/odd > - Add in all the restrictions from DIV A,B from the hardware manual > - No more need to be a recursive function > - DPI settings must have DSI_DIV_B be '0' (divide 1/1) > --- > drivers/clk/renesas/rzg2l-cpg.c | 147 +++++++++++++++++++++++++++++--- > include/linux/clk/renesas.h | 12 +++ > 2 files changed, 146 insertions(+), 13 deletions(-) > > diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c > index 07909e80bae2..1a552ea1c535 100644 > --- a/drivers/clk/renesas/rzg2l-cpg.c > +++ b/drivers/clk/renesas/rzg2l-cpg.c > @@ -74,6 +74,17 @@ > #define MSTOP_OFF(conf) FIELD_GET(GENMASK(31, 16), (conf)) > #define MSTOP_MASK(conf) FIELD_GET(GENMASK(15, 0), (conf)) > > > + if (dsi_div_target == PLL5_TARGET_DPI) { > + /* Fixed settings for DPI */ > + priv->mux_dsi_div_params.clksrc = 0; > + priv->mux_dsi_div_params.dsi_div_a = 3; /* Divided by 8 */ > + priv->mux_dsi_div_params.dsi_div_b = 0; /* Divided by 1 */ > + dsi_div_ab_desired = 8; /* (1 << a) * (b + 1) > */ This block is duplicated may be add a helper function(), if you are planning to send another series. > + } > + /* Default settings for DPI */ > + priv->mux_dsi_div_params.clksrc = 0; > + priv->mux_dsi_div_params.dsi_div_a = 3; /* Divided by 8 */ > + priv->mux_dsi_div_params.dsi_div_b = 0; /* Divided by 1 */ > + dsi_div_ab_desired = 8; /* (1 << a) * (b + 1) */ > Cheers, Biju
