> Subject: [v5 21/24] drm/i915/xelpd: Program Plane Post CSC Registers > > From: Chaitanya Kumar Borah <[email protected]> > > Extract the LUT and program plane post csc registers. > > v2: Add DSB support > v3: Add support for single segment 1D LUT >
Add Bspec link here > Signed-off-by: Uma Shankar <[email protected]> > Signed-off-by: Chaitanya Kumar Borah <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_color.c | 123 +++++++++++++++++++++ > 1 file changed, 123 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_color.c > b/drivers/gpu/drm/i915/display/intel_color.c > index 75981fe232bf..689bc4f4ce25 100644 > --- a/drivers/gpu/drm/i915/display/intel_color.c > +++ b/drivers/gpu/drm/i915/display/intel_color.c > @@ -4041,11 +4041,134 @@ xelpd_program_plane_pre_csc_lut(struct > intel_dsb *dsb, > } > } > > +static void > +xelpd_program_plane_post_csc_lut(struct intel_dsb *dsb, > + const struct intel_plane_state *plane_state) { > + struct intel_display *display = to_intel_display(plane_state); > + const struct drm_plane_state *state = &plane_state->uapi; > + enum pipe pipe = to_intel_plane(state->plane)->pipe; > + enum plane_id plane = to_intel_plane(state->plane)->id; > + const struct drm_color_lut_32 *post_csc_lut = plane_state- > >hw.gamma_lut->data; > + u32 i, lut_size, j; > + bool is_single_seg = drm_color_lut_32_size(plane_state- > >hw.gamma_lut) == 32 ? > + true : false; > + > + if (icl_is_hdr_plane(display, plane)) { > + intel_de_write_dsb(display, dsb, > PLANE_POST_CSC_GAMC_INDEX_ENH(pipe, plane, 0), > + PLANE_PAL_PREC_AUTO_INCREMENT); > + /* TODO: Add macro */ > + intel_de_write_dsb(display, dsb, > PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH(pipe, plane, 0), > + PLANE_PAL_PREC_AUTO_INCREMENT); > + if (post_csc_lut) { > + /* Segment 0 */ > + for (i = 0, j = 0; i < 9; i++, j++) { > + if (is_single_seg) > + break; > + > + u32 lut_val = (post_csc_lut[j].green & > 0xffffff); We do not do a declaration like this in the middle. Also I would suggest having it declared higher and zero is when reassignment is needed since it seems to be used in almost every code block. Regards, Suraj Kandpal > + > + intel_de_write_dsb(display, dsb, > + > PLANE_POST_CSC_GAMC_SEG0_DATA_ENH(pipe, > + > plane, 0), > + lut_val); > + } > + > + /* Segment 1 */ > + lut_size = 32; > + for (i = 0; i < lut_size; i++) { > + u32 lut_val; > + > + if (i == 0 && !is_single_seg) > + lut_val = post_csc_lut[0].green & > 0xffffff; > + else if (i == 1 && !is_single_seg) > + lut_val = (post_csc_lut[8].green & > 0xffffff); > + else > + lut_val = is_single_seg ? > + > drm_color_lut_32_extract(post_csc_lut[j++].green, > + 24) > + : (post_csc_lut[j++].green & > 0xffffff); > + > + intel_de_write_dsb(display, dsb, > + > PLANE_POST_CSC_GAMC_DATA_ENH(pipe, plane, 0), > + lut_val); > + } > + > + /* Segment 2 */ > + do { > + intel_de_write_dsb(display, dsb, > + > PLANE_POST_CSC_GAMC_DATA_ENH(pipe, plane, 0), > + is_single_seg ? (1 << 24) : > + post_csc_lut[j].green); > + } while (++j < (is_single_seg ? 34 : 42)); > + } else { > + /*TODO: Add for segment 0 */ > + lut_size = 32; > + for (i = 0; i < lut_size; i++) { > + u32 v = (i * ((1 << 24) - 1)) / (lut_size - 1); > + > + intel_de_write_dsb(display, dsb, > + > PLANE_POST_CSC_GAMC_DATA_ENH(pipe, plane, 0), v); > + } > + > + do { > + intel_de_write_dsb(display, dsb, > + > PLANE_POST_CSC_GAMC_DATA_ENH(pipe, plane, 0), > + 1 << 24); > + } while (i++ < 34); > + } > + > + intel_de_write_dsb(display, dsb, > PLANE_POST_CSC_GAMC_INDEX_ENH(pipe, plane, 0), 0); > + intel_de_write_dsb(display, dsb, > + > PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH(pipe, plane, 0), 0); > + } else { > + lut_size = 32; > + /* > + * First 3 planes are HDR, so reduce by 3 to get to the right > + * SDR plane offset > + */ > + plane = plane - 3; > + > + intel_de_write_dsb(display, dsb, > PLANE_POST_CSC_GAMC_INDEX(pipe, plane, 0), > + PLANE_PAL_PREC_AUTO_INCREMENT); > + > + if (post_csc_lut) { > + for (i = 0; i < lut_size; i++) > + intel_de_write_dsb(display, dsb, > + > PLANE_POST_CSC_GAMC_DATA(pipe, plane, 0), > + post_csc_lut[i].green & > 0xffff); > + /* Program the max register to clamp values > 1.0. */ > + while (i < 35) > + intel_de_write_dsb(display, dsb, > + > PLANE_POST_CSC_GAMC_DATA(pipe, plane, 0), > + post_csc_lut[i++].green & > 0x3ffff); > + } else { > + for (i = 0; i < lut_size; i++) { > + u32 v = (i * ((1 << 16) - 1)) / (lut_size - 1); > + > + intel_de_write_dsb(display, dsb, > + > PLANE_POST_CSC_GAMC_DATA(pipe, plane, 0), v); > + } > + > + do { > + intel_de_write_dsb(display, dsb, > + > PLANE_POST_CSC_GAMC_DATA(pipe, plane, 0), > + (1 << 16)); > + } while (i++ < 34); > + } > + > + intel_de_write_dsb(display, dsb, > PLANE_POST_CSC_GAMC_INDEX(pipe, plane, 0), 0); > + } > +} > + > static void > xelpd_plane_load_luts(struct intel_dsb *dsb, const struct intel_plane_state > *plane_state) { > if (plane_state->hw.degamma_lut) > xelpd_program_plane_pre_csc_lut(dsb, plane_state); > + > + if (plane_state->hw.gamma_lut) > + xelpd_program_plane_post_csc_lut(dsb, plane_state); > } > > static const struct intel_color_funcs chv_color_funcs = { > -- > 2.42.0
