On 10/27/25 17:41, Paul Walmsley wrote:
> On Mon, 27 Oct 2025, Christian König wrote:
>
>> On 10/20/25 07:35, Icenowy Zheng wrote:
>>> The RISC-V Svpbmt privileged extension provides support for overriding
>>> page memory coherency attributes, and, along with vendor extensions like
>>> Xtheadmae, supports pgprot_{writecombine,noncached} on RISC-V.
>>>
>>> Adapt the codepath that maps ttm_write_combined to pgprot_writecombine
>>> and ttm_noncached to pgprot_noncached to RISC-V, to allow proper page
>>> access attributes.
>
> [ ... ]
>
>>> diff --git a/drivers/gpu/drm/ttm/ttm_module.c
>>> b/drivers/gpu/drm/ttm/ttm_module.c
>>> index b3fffe7b5062a..aa137ead5cc59 100644
>>> --- a/drivers/gpu/drm/ttm/ttm_module.c
>>> +++ b/drivers/gpu/drm/ttm/ttm_module.c
>>> @@ -74,7 +74,8 @@ pgprot_t ttm_prot_from_caching(enum ttm_caching caching,
>>> pgprot_t tmp)
>>> #endif /* CONFIG_UML */
>>> #endif /* __i386__ || __x86_64__ */
>>> #if defined(__ia64__) || defined(__arm__) || defined(__aarch64__) || \
>>> - defined(__powerpc__) || defined(__mips__) || defined(__loongarch__)
>>> + defined(__powerpc__) || defined(__mips__) || defined(__loongarch__) || \
>>> + defined(__riscv)
>>
>> Looks reasonable, but does that work on all RISC-V variants?
>
> From an RISC-V architectural perspective, yes.
>
> Of course there might be a hardware bug in some given manufacturer's
> implementation, but then again, that could happen on the other
> architectures as well.
I've added my acked-by and pushed it to drm-misc-next.
Regards,
Christian.
>
>
> - Paul
