On Thu, Oct 23, 2025 at 03:17:53PM +0300, Dmitry Baryshkov wrote: > On Thu, Oct 23, 2025 at 04:17:36PM +0800, yuanjie yang wrote: > > From: Yuanjie Yang <[email protected]> > > > > Add MDSS/MDP display subsystem for Qualcomm Kaanapali. > > > > Signed-off-by: Yongxing Mou <[email protected]> > > Signed-off-by: Yuanjie Yang <[email protected]> > > --- > > .../display/msm/qcom,kaanapali-mdss.yaml | 298 ++++++++++++++++++ > > 1 file changed, 298 insertions(+) > > create mode 100644 > > Documentation/devicetree/bindings/display/msm/qcom,kaanapali-mdss.yaml > > > > + > > + "^phy@[0-9a-f]+$": > > + type: object > > + additionalProperties: true > > + properties: > > + compatible: > > + const: qcom,kaanapali-dsi-phy-3nm > > + > > +required: > > + - compatible > > + > > +unevaluatedProperties: false > > + > > + > > + mdss_dsi0_phy: phy@ae95000 { > > + compatible = "qcom,kaanapali-dsi-phy-3nm", > > "qcom,sm8750-dsi-phy-3nm"; > > This doesn't match what you've written above. Was it validated? Thanks for your reminder, this is a mistake forget to fix.
correct here: compatible = "qcom,kaanapali-dsi-phy-3nm"; qcom,kaanapali-dsi-phy-3nm and qcom,sm8750-dsi-phy-3nm have different cfg. Will be more careful to push a better patch. Thanks for your careful review. Thanks, Yuanjie > > + reg = <0x09ac1000 0x200>, > > + <0x09ac1200 0x280>, > > + <0x09ac1500 0x400>; > > + reg-names = "dsi_phy", > > + "dsi_phy_lane", > > + "dsi_pll"; > > + > > + clocks = <&disp_cc_mdss_ahb_clk>, > > + <&rpmhcc RPMH_CXO_CLK>; > > + clock-names = "iface", > > + "ref"; > > + > > + vdds-supply = <&vreg_l3i_0p88>; > > + > > + #clock-cells = <1>; > > + #phy-cells = <0>; > > + }; > > + }; > > -- > > 2.34.1 > > > > -- > With best wishes > Dmitry
