> It would be good to switch both of these for consistency with the > other chips, but the rationale for this is not quite correct. > PCIeBootLinkLevel is supposed to represent the level the link was > trained at when the system booted.
I see, didn't know about that. > If this does make a difference for you, > then you may have a platform which does not support dynamic gen > switching in which case, you'd be stuck at the boot level. No clue, this is the only Fiji card that I have and the only card that exhibits this behaviour, my Polaris card and a Nvidia card that I have spare do the switching just fine... > Please send this patch along with the patch for iceland and I'll apply them. Will do. On Mon, Oct 20, 2025 at 8:00 PM Alex Deucher <[email protected]> wrote: > > On Mon, Oct 20, 2025 at 10:21 AM John Smith <[email protected]> wrote: > > > > Fiji seems to have difficulty with switching PCIe generations > > including on my Instinct MI8, where it is basically stuck at Gen 1 > > unless manually switched by using a different PowerPlay profile. > > (using the pp_dpm_pcie sysfs does not work) > > > > 18edef19ea44 introduced support for Fiji's SMU, which included setting > > the PCIeBootLinkLevel value to zero which is equal to PCI Express Gen > > 1. > > > > By copying what Tonga and other generations of AMD GPUs do, which is > > to use the maximum value from the speed table, fixes the issue. > > > > (p.s. I believe Topaz's SMU also has the same issue, I can send in an > > additional patch if needed) > > It would be good to switch both of these for consistency with the > other chips, but the rationale for this is not quite correct. > PCIeBootLinkLevel is supposed to represent the level the link was > trained at when the system booted. We should read the current level > from PCI config space, however, it was changed to > pcie_speed_table.count because after a driver unload and reload, the > PCIe level will end up at gen 1 because the firmware will put it there > when the driver was previously loaded. I don't think the boot link > level affects PCIe at runtime. IIRC, the PCIe gen levels are > determined based on PCIe caps and whether the platform supports > dynamic PCIe gen switching. If this does make a difference for you, > then you may have a platform which does not support dynamic gen > switching in which case, you'd be stuck at the boot level. Please > send this patch along with the patch for iceland and I'll apply them. > > Thanks! > > Alex > > > > > Fixes: 18edef19ea44 ("drm/amd/powerplay: implement fw image related > > smu interface for Fiji.") > > Signed-off-by: John Smith <[email protected]> > > --- > > drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c > > b/drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c > > index d2dbd90bb427..0a876c840c79 100644 > > --- a/drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c > > +++ b/drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c > > @@ -2024,7 +2024,7 @@ static int fiji_init_smc_table(struct pp_hwmgr *hwmgr) > > table->VoltageResponseTime = 0; > > table->PhaseResponseTime = 0; > > table->MemoryThermThrottleEnable = 1; > > - table->PCIeBootLinkLevel = 0; /* 0:Gen1 1:Gen2 2:Gen3*/ > > + table->PCIeBootLinkLevel = (uint8_t) > > (data->dpm_table.pcie_speed_table.count); > > table->PCIeGenInterval = 1; > > table->VRConfig = 0;
