On Wednesday, October 8, 2025 4:30 PM Svyatoslav Ryhel wrote:
> Add CSI node to Tegra20 and Tegra30 device trees.
> 
> Signed-off-by: Svyatoslav Ryhel <[email protected]>
> ---
>  arch/arm/boot/dts/nvidia/tegra20.dtsi | 19 ++++++++++++++++++-
>  arch/arm/boot/dts/nvidia/tegra30.dtsi | 24 ++++++++++++++++++++++--
>  2 files changed, 40 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/nvidia/tegra20.dtsi 
> b/arch/arm/boot/dts/nvidia/tegra20.dtsi
> index 6ae07b316c8a..5cdbf1246cf8 100644
> --- a/arch/arm/boot/dts/nvidia/tegra20.dtsi
> +++ b/arch/arm/boot/dts/nvidia/tegra20.dtsi
> @@ -64,7 +64,7 @@ mpe@54040000 {
>  
>               vi@54080000 {
>                       compatible = "nvidia,tegra20-vi";
> -                     reg = <0x54080000 0x00040000>;
> +                     reg = <0x54080000 0x00000800>;
>                       interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
>                       clocks = <&tegra_car TEGRA20_CLK_VI>;
>                       resets = <&tegra_car 20>;
> @@ -72,6 +72,23 @@ vi@54080000 {
>                       power-domains = <&pd_venc>;
>                       operating-points-v2 = <&vi_dvfs_opp_table>;
>                       status = "disabled";
> +
> +                     #address-cells = <1>;
> +                     #size-cells = <1>;
> +
> +                     ranges = <0x0 0x54080000 0x4000>;
> +
> +                     csi: csi@800 {
> +                             compatible = "nvidia,tegra20-csi";
> +                             reg = <0x800 0x200>;
> +                             clocks = <&tegra_car TEGRA20_CLK_CSI>;
> +                             power-domains = <&pd_venc>;
> +                             #nvidia,mipi-calibrate-cells = <1>;
> +                             status = "disabled";
> +
> +                             #address-cells = <1>;
> +                             #size-cells = <0>;
> +                     };
>               };
>  
>               epp@540c0000 {
> diff --git a/arch/arm/boot/dts/nvidia/tegra30.dtsi 
> b/arch/arm/boot/dts/nvidia/tegra30.dtsi
> index 20b3248d4d2f..be752a245a55 100644
> --- a/arch/arm/boot/dts/nvidia/tegra30.dtsi
> +++ b/arch/arm/boot/dts/nvidia/tegra30.dtsi
> @@ -150,8 +150,8 @@ mpe@54040000 {
>               };
>  
>               vi@54080000 {
> -                     compatible = "nvidia,tegra30-vi";
> -                     reg = <0x54080000 0x00040000>;
> +                     compatible = "nvidia,tegra30-vi", "nvidia,tegra20-vi";
> +                     reg = <0x54080000 0x00000800>;
>                       interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
>                       clocks = <&tegra_car TEGRA30_CLK_VI>;
>                       resets = <&tegra_car 20>;
> @@ -162,6 +162,26 @@ vi@54080000 {
>                       iommus = <&mc TEGRA_SWGROUP_VI>;
>  
>                       status = "disabled";
> +
> +                     #address-cells = <1>;
> +                     #size-cells = <1>;
> +
> +                     ranges = <0x0 0x54080000 0x4000>;
> +
> +                     csi: csi@800 {
> +                             compatible = "nvidia,tegra30-csi";
> +                             reg = <0x800 0x200>;
> +                             clocks = <&tegra_car TEGRA30_CLK_CSI>,
> +                                      <&tegra_car TEGRA30_CLK_CSIA_PAD>,
> +                                      <&tegra_car TEGRA30_CLK_CSIB_PAD>;
> +                             clock-names = "csi", "csia-pad", "csib-pad";
> +                             power-domains = <&pd_venc>;
> +                             #nvidia,mipi-calibrate-cells = <1>;
> +                             status = "disabled";
> +
> +                             #address-cells = <1>;
> +                             #size-cells = <0>;
> +                     };
>               };
>  
>               epp@540c0000 {
> 

Reviewed-by: Mikko Perttunen <[email protected]>




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