Am Mittwoch, 3. September 2025, 20:51:00 Mitteleuropäische Sommerzeit schrieb Cristian Ciocaltea: > Currently the TIMER_BASE_CONFIG0 register gets initialized to a fixed > value as initially found in vendor driver code supporting the RK3588 > SoC. As a matter of fact the value matches the rate of the HDMI TX > reference clock, which is roughly 428.57 MHz. > > However, on RK3576 SoC that rate is slightly lower, i.e. 396.00 MHz, and > the incorrect register configuration breaks CEC functionality. > > Set the timer base according to the actual reference clock rate that > shall be provided by the platform driver. Otherwise fallback to the > vendor default. > > While at it, also drop the unnecessary empty lines in > dw_hdmi_qp_init_hw(). > > Signed-off-by: Cristian Ciocaltea <[email protected]>
Reviewed-by: Heiko Stuebner <[email protected]> This _does_ look ok to me, but as that touches the main bridge, could we get a 2nd set of eyes? Thanks Heiko > --- > drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c | 12 +++++++++--- > include/drm/bridge/dw_hdmi_qp.h | 1 + > 2 files changed, 10 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c > b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c > index > fc98953672b6fb388d05201e280d24b8f214498a..4ba7b339eff62592aa748429a3bfca82494679d1 > 100644 > --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c > +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c > @@ -161,6 +161,7 @@ struct dw_hdmi_qp { > void *data; > } phy; > > + unsigned long ref_clk_rate; > struct regmap *regm; > > unsigned long tmds_char_rate; > @@ -1210,13 +1211,11 @@ static void dw_hdmi_qp_init_hw(struct dw_hdmi_qp > *hdmi) > { > dw_hdmi_qp_write(hdmi, 0, MAINUNIT_0_INT_MASK_N); > dw_hdmi_qp_write(hdmi, 0, MAINUNIT_1_INT_MASK_N); > - dw_hdmi_qp_write(hdmi, 428571429, TIMER_BASE_CONFIG0); > + dw_hdmi_qp_write(hdmi, hdmi->ref_clk_rate, TIMER_BASE_CONFIG0); > > /* Software reset */ > dw_hdmi_qp_write(hdmi, 0x01, I2CM_CONTROL0); > - > dw_hdmi_qp_write(hdmi, 0x085c085c, I2CM_FM_SCL_CONFIG0); > - > dw_hdmi_qp_mod(hdmi, 0, I2CM_FM_EN, I2CM_INTERFACE_CONTROL0); > > /* Clear DONE and ERROR interrupts */ > @@ -1262,6 +1261,13 @@ struct dw_hdmi_qp *dw_hdmi_qp_bind(struct > platform_device *pdev, > hdmi->phy.ops = plat_data->phy_ops; > hdmi->phy.data = plat_data->phy_data; > > + if (plat_data->ref_clk_rate) { > + hdmi->ref_clk_rate = plat_data->ref_clk_rate; > + } else { > + hdmi->ref_clk_rate = 428571429; > + dev_warn(dev, "Set ref_clk_rate to vendor default\n"); > + } > + > dw_hdmi_qp_init_hw(hdmi); > > ret = devm_request_threaded_irq(dev, plat_data->main_irq, > diff --git a/include/drm/bridge/dw_hdmi_qp.h b/include/drm/bridge/dw_hdmi_qp.h > index > b4a9b739734ec7b67013b683fe6017551aa19172..76ecf31301997718604a05f70ce9eab8695e26b5 > 100644 > --- a/include/drm/bridge/dw_hdmi_qp.h > +++ b/include/drm/bridge/dw_hdmi_qp.h > @@ -24,6 +24,7 @@ struct dw_hdmi_qp_plat_data { > void *phy_data; > int main_irq; > int cec_irq; > + unsigned long ref_clk_rate; > }; > > struct dw_hdmi_qp *dw_hdmi_qp_bind(struct platform_device *pdev, > >
