On Tue, Sep 30, 2025 at 11:18:07AM +0530, Akhil P Oommen wrote: > Correct the register offset and enable this workaround for all A7x > and newer GPUs to match downstream. Also, downstream does this w/a after > moving the fence to allow mode. So do the same.
Please adopt the 'why' style of commit messages. Describe the issue, then describe what needs to be done. > > Signed-off-by: Akhil P Oommen <[email protected]> > --- > drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > index > fc62fef2fed87f065cb8fa4e997abefe4ff11cd5..e22106cafc394ef85f060e4f70596e55c3ec39a4 > 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > @@ -485,8 +485,9 @@ static void a6xx_gemnoc_workaround(struct a6xx_gmu *gmu) > * in the power down sequence not being fully executed. That in turn can > * prevent CX_GDSC from collapsing. Assert Qactive to avoid this. > */ > - if (adreno_is_a621(adreno_gpu) || adreno_is_7c3(adreno_gpu)) > - gmu_write(gmu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, BIT(0)); > + if (adreno_is_a7xx(adreno_gpu) || (adreno_is_a621(adreno_gpu) || > + adreno_is_7c3(adreno_gpu))) > + gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_CX_FALNEXT_INTF, BIT(0)); > } > > /* Let the GMU know that we are about to go into slumber */ > @@ -522,10 +523,9 @@ static int a6xx_gmu_notify_slumber(struct a6xx_gmu *gmu) > } > > out: > - a6xx_gemnoc_workaround(gmu); > - > /* Put fence into allow mode */ > gmu_write(gmu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, 0); > + a6xx_gemnoc_workaround(gmu); > return ret; > } > > > -- > 2.51.0 > -- With best wishes Dmitry
