On Tue, Sep 30, 2025 at 02:38:09PM +0300, Imre Deak wrote: > On Tue, Sep 30, 2025 at 08:30:10AM +0300, Dmitry Baryshkov wrote: > > On Mon, Sep 29, 2025 at 01:10:17PM +0300, Imre Deak wrote: > > > On Mon, Sep 29, 2025 at 12:00:03PM +0300, Dmitry Baryshkov wrote: > > > > On Mon, Sep 29, 2025 at 09:36:44AM +0300, Imre Deak wrote: > > > > > Add helpers to query the DP DSC sink device's per-slice throughput as > > > > > well as a DSC branch device's overall throughput and line-width > > > > > capabilities. > > > > > > > > > > v2 (Ville): > > > > > - Rename pixel_clock to peak_pixel_rate, document what the value means > > > > > in case of MST tiled displays. > > > > > - Fix name of drm_dp_dsc_branch_max_slice_throughput() to > > > > > drm_dp_dsc_sink_max_slice_throughput(). > > > > > v3: > > > > > - Fix the DSC branch device minimum valid line width value from 2560 > > > > > to 5120 pixels. > > > > > - Fix drm_dp_dsc_sink_max_slice_throughput()'s pixel_clock parameter > > > > > name to peak_pixel_rate in header file. > > > > > - Add handling for throughput mode 0 granular delta, defined by DP > > > > > Standard v2.1a. > > > > > > > > This one got sent as a separate V5, without a proper changelog. What has > > > > changed? > > > > > > This is v3 of the patch, the changes are listed under v3. The patchset's > > > version is v5. > > > > Ugh. How one does relate this v3 (which is not mentioned anywhere) and > > v5 of the series? This is totally counterintuitive. A usual > > recommendation is to send the full series and to send it as a new > > thread, sending all the patches in one go. > > It's a common practice on intel-gfx to send a new version of one patch > on top of the last patchset version in that patchset's thread. For
I don't want to step on intel-gfx ways of working, but how would that work with e.g. 'b4 shazam'? > matching the patch version to the patchset version I can change the > patch version log above to be like: > > v2 (Ville): > - Rename pixel_clock to peak_pixel_rate ... > v3-v4: > - No changes > v5: > - Fix the DSC branch device minimum valid line width value ... Yes, I think that's more obvious, thanks! > > > > > > Cc: [email protected] > > > > > Suggested-by: Ville Syrjälä <[email protected]> > > > > > Signed-off-by: Imre Deak <[email protected]> > > > > > --- > > > > > drivers/gpu/drm/display/drm_dp_helper.c | 156 > > > > > ++++++++++++++++++++++++ > > > > > include/drm/display/drm_dp.h | 3 + > > > > > include/drm/display/drm_dp_helper.h | 5 + > > > > > 3 files changed, 164 insertions(+) > > > > > > > > > > > > > -- > > > > With best wishes > > > > Dmitry > > > > -- > > With best wishes > > Dmitry -- With best wishes Dmitry
