On Mon, Sep 29, 2025 at 12:47 AM Nicolas Frattaroli
<[email protected]> wrote:
>
> The MT8196 SoC uses an embedded MCU to control frequencies and power of
> the GPU. This controller is referred to as "GPUEB".
>
> It communicates to the application processor, among other ways, through
> a mailbox.
>
> The mailbox exposes one interrupt, which appears to only be fired when a
> response is received, rather than a transaction is completed. For us,
> this means we unfortunately need to poll for txdone.
>
> The mailbox also requires the EB clock to be on when touching any of the
> mailbox registers.
>
> Add a simple driver for it based on the common mailbox framework.
>
> Reviewed-by: AngeloGioacchino Del Regno
> <[email protected]>
> Signed-off-by: Nicolas Frattaroli <[email protected]>
Reviewed-by: Chia-I Wu <[email protected]>
> ---
> drivers/mailbox/Kconfig | 10 ++
> drivers/mailbox/Makefile | 2 +
> drivers/mailbox/mtk-gpueb-mailbox.c | 318
> ++++++++++++++++++++++++++++++++++++
> 3 files changed, 330 insertions(+)
[...]
> +static irqreturn_t mtk_gpueb_mbox_thread(int irq, void *data)
> +{
> + struct mtk_gpueb_mbox_chan *ch = data;
> + u8 buf[GPUEB_MBOX_MAX_RX_SIZE] = {};
nit: move to inside the if-block below.
> + int status;
> +
> + status = atomic_cmpxchg(&ch->rx_status, GPUEB_MBOX_FULL |
> GPUEB_MBOX_BLOCKED,
> + GPUEB_MBOX_FULL);
> + if (status == (GPUEB_MBOX_FULL | GPUEB_MBOX_BLOCKED)) {
> + mtk_gpueb_mbox_read_rx(buf, ch);
> + writel(BIT(ch->num), ch->ebm->mbox_ctl +
> GPUEB_MBOX_CTL_IRQ_CLR);
> + mbox_chan_received_data(&ch->ebm->mbox.chans[ch->num], buf);
> + atomic_set(&ch->rx_status, 0);
> + return IRQ_HANDLED;
> + }
> +
> + return IRQ_NONE;
> +}
