Hi Imre, Thanks for the fix. Validated with Dell WD 19TB and LG 40WP95-C
Tested-by: Swati Sharma <[email protected]> On 27-09-2025 02:42 am, Imre Deak wrote:
This is v4 of [1], with the following changes: - Fix drm_dp_dsc_sink_max_slice_throughput()'s name. - Use the clearer peak_pixel_rate vs. pixel_clock as the above function's parameter. - Clarify the meaning of peak_pixel_rate for MST tiled displays. - Fix return value from dsc_throughput_quirk_max_bpp_x16(), in case it's not required to limit the BPP. [1] https://lore.kernel.org/all/[email protected] Reported-by: Vidya Srinivas <[email protected]> Reported-by: Swati Sharma <[email protected]> Cc: Ville Syrjälä <[email protected]> Cc: [email protected] Imre Deak (6): drm/dp: Add quirk for Synaptics DSC throughput link-bpp limit drm/dp: Add helpers to query the branch DSC max throughput/line-width drm/i915/dp: Calculate DSC slice count based on per-slice peak throughput drm/i915/dp: Pass DPCD device descriptor to intel_dp_get_dsc_sink_cap() drm/i915/dp: Verify branch devices' overall pixel throughput/line width drm/i915/dp: Handle Synaptics DSC throughput link-bpp quirk drivers/gpu/drm/display/drm_dp_helper.c | 146 ++++++++++++++++++ .../drm/i915/display/intel_display_types.h | 9 ++ drivers/gpu/drm/i915/display/intel_dp.c | 146 ++++++++++++++++-- drivers/gpu/drm/i915/display/intel_dp.h | 5 +- drivers/gpu/drm/i915/display/intel_dp_mst.c | 9 +- include/drm/display/drm_dp.h | 1 + include/drm/display/drm_dp_helper.h | 14 ++ 7 files changed, 316 insertions(+), 14 deletions(-)
