The GSP requires several areas of memory to operate. Each of these have their own simple embedded page tables. Set these up and map them for DMA to/from GSP using CoherentAllocation's. Return the DMA handle describing where each of these regions are for future use when booting GSP.
Signed-off-by: Alistair Popple <[email protected]> --- Changes for v2: - Renamed GspMemOjbects to Gsp as that is what they are - Rebased on Alex's latest series --- drivers/gpu/nova-core/gpu.rs | 2 +- drivers/gpu/nova-core/gsp.rs | 80 +++++++++++++++++-- drivers/gpu/nova-core/gsp/fw.rs | 39 +++++++++ .../gpu/nova-core/gsp/fw/r570_144/bindings.rs | 19 +++++ 4 files changed, 131 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/nova-core/gpu.rs b/drivers/gpu/nova-core/gpu.rs index 5da9ad726483..c939b3868271 100644 --- a/drivers/gpu/nova-core/gpu.rs +++ b/drivers/gpu/nova-core/gpu.rs @@ -221,7 +221,7 @@ pub(crate) fn new<'a>( sec2_falcon: Falcon::new(pdev.as_ref(), spec.chipset, bar, true)?, - gsp <- Gsp::new(), + gsp <- Gsp::new(pdev)?, _: { gsp.boot(pdev, bar, spec.chipset, gsp_falcon, sec2_falcon)? }, diff --git a/drivers/gpu/nova-core/gsp.rs b/drivers/gpu/nova-core/gsp.rs index 503ce8ee0420..0185f66971ff 100644 --- a/drivers/gpu/nova-core/gsp.rs +++ b/drivers/gpu/nova-core/gsp.rs @@ -1,27 +1,91 @@ // SPDX-License-Identifier: GPL-2.0 mod boot; - -use kernel::prelude::*; - mod fw; pub(crate) use fw::{GspFwWprMeta, LibosParams}; +use kernel::device; +use kernel::dma::CoherentAllocation; +use kernel::dma_write; +use kernel::pci; +use kernel::prelude::*; use kernel::ptr::Alignment; +use kernel::transmute::{AsBytes, FromBytes}; + +use fw::LibosMemoryRegionInitArgument; pub(crate) const GSP_PAGE_SHIFT: usize = 12; pub(crate) const GSP_PAGE_SIZE: usize = 1 << GSP_PAGE_SHIFT; pub(crate) const GSP_HEAP_ALIGNMENT: Alignment = Alignment::new::<{ 1 << 20 }>(); /// GSP runtime data. -/// -/// This is an empty pinned placeholder for now. #[pin_data] -pub(crate) struct Gsp {} +pub(crate) struct Gsp { + libos: CoherentAllocation<LibosMemoryRegionInitArgument>, + pub loginit: CoherentAllocation<u8>, + pub logintr: CoherentAllocation<u8>, + pub logrm: CoherentAllocation<u8>, +} + +/// Creates a self-mapping page table for `obj` at its beginning. +fn create_pte_array(obj: &mut CoherentAllocation<u8>) { + let num_pages = obj.size().div_ceil(GSP_PAGE_SIZE); + let handle = obj.dma_handle(); + + // SAFETY: + // - By the invariants of the CoherentAllocation ptr is non-NULL. + // - CoherentAllocation CPU addresses are always aligned to a + // page-boundary, satisfying the alignment requirements for + // from_raw_parts_mut() + // - The allocation size is at least as long as 8 * num_pages as + // GSP_PAGE_SIZE is larger than 8 bytes. + let ptes = unsafe { + let ptr = obj.start_ptr_mut().cast::<u64>().add(1); + core::slice::from_raw_parts_mut(ptr, num_pages) + }; + + for (i, pte) in ptes.iter_mut().enumerate() { + *pte = handle + ((i as u64) << GSP_PAGE_SHIFT); + } +} + +/// Creates a new `CoherentAllocation<A>` with `name` of `size` elements, and +/// register it into the `libos` object at argument position `libos_arg_nr`. +fn create_coherent_dma_object<A: AsBytes + FromBytes>( + dev: &device::Device<device::Bound>, + name: &'static str, + size: usize, + libos: &mut CoherentAllocation<LibosMemoryRegionInitArgument>, + libos_arg_nr: usize, +) -> Result<CoherentAllocation<A>> { + let obj = CoherentAllocation::<A>::alloc_coherent(dev, size, GFP_KERNEL | __GFP_ZERO)?; + + dma_write!(libos[libos_arg_nr] = LibosMemoryRegionInitArgument::new(name, &obj))?; + + Ok(obj) +} impl Gsp { - pub(crate) fn new() -> impl PinInit<Self> { - pin_init!(Self {}) + pub(crate) fn new(pdev: &pci::Device<device::Bound>) -> Result<impl PinInit<Self, Error>> { + let dev = pdev.as_ref(); + let mut libos = CoherentAllocation::<LibosMemoryRegionInitArgument>::alloc_coherent( + dev, + GSP_PAGE_SIZE / size_of::<LibosMemoryRegionInitArgument>(), + GFP_KERNEL | __GFP_ZERO, + )?; + let mut loginit = create_coherent_dma_object::<u8>(dev, "LOGINIT", 0x10000, &mut libos, 0)?; + create_pte_array(&mut loginit); + let mut logintr = create_coherent_dma_object::<u8>(dev, "LOGINTR", 0x10000, &mut libos, 1)?; + create_pte_array(&mut logintr); + let mut logrm = create_coherent_dma_object::<u8>(dev, "LOGRM", 0x10000, &mut libos, 2)?; + create_pte_array(&mut logrm); + + Ok(try_pin_init!(Self { + libos, + loginit, + logintr, + logrm, + })) } } diff --git a/drivers/gpu/nova-core/gsp/fw.rs b/drivers/gpu/nova-core/gsp/fw.rs index 181baa401770..dd1e7fc85d85 100644 --- a/drivers/gpu/nova-core/gsp/fw.rs +++ b/drivers/gpu/nova-core/gsp/fw.rs @@ -7,8 +7,10 @@ use core::ops::Range; +use kernel::dma::CoherentAllocation; use kernel::ptr::Alignable; use kernel::sizes::SZ_1M; +use kernel::transmute::{AsBytes, FromBytes}; use crate::gpu::Chipset; use crate::gsp; @@ -99,3 +101,40 @@ pub(crate) fn wpr_heap_size(&self, chipset: Chipset, fb_size: u64) -> u64 { /// addresses of the GSP bootloader and firmware. #[repr(transparent)] pub(crate) struct GspFwWprMeta(bindings::GspFwWprMeta); + +#[repr(transparent)] +pub(crate) struct LibosMemoryRegionInitArgument(bindings::LibosMemoryRegionInitArgument); + +// SAFETY: Padding is explicit and will not contain uninitialized data. +unsafe impl AsBytes for LibosMemoryRegionInitArgument {} + +// SAFETY: This struct only contains integer types for which all bit patterns +// are valid. +unsafe impl FromBytes for LibosMemoryRegionInitArgument {} + +impl LibosMemoryRegionInitArgument { + pub(crate) fn new<A: AsBytes + FromBytes>( + name: &'static str, + obj: &CoherentAllocation<A>, + ) -> Self { + /// Generates the `ID8` identifier required for some GSP objects. + fn id8(name: &str) -> u64 { + let mut bytes = [0u8; core::mem::size_of::<u64>()]; + + for (c, b) in name.bytes().rev().zip(&mut bytes) { + *b = c; + } + + u64::from_ne_bytes(bytes) + } + + Self(bindings::LibosMemoryRegionInitArgument { + id8: id8(name), + pa: obj.dma_handle(), + size: obj.size() as u64, + kind: bindings::LibosMemoryRegionKind_LIBOS_MEMORY_REGION_CONTIGUOUS as u8, + loc: bindings::LibosMemoryRegionLoc_LIBOS_MEMORY_REGION_LOC_SYSMEM as u8, + ..Default::default() + }) + } +} diff --git a/drivers/gpu/nova-core/gsp/fw/r570_144/bindings.rs b/drivers/gpu/nova-core/gsp/fw/r570_144/bindings.rs index 0407000cca22..6a14cc324391 100644 --- a/drivers/gpu/nova-core/gsp/fw/r570_144/bindings.rs +++ b/drivers/gpu/nova-core/gsp/fw/r570_144/bindings.rs @@ -124,3 +124,22 @@ fn default() -> Self { } } } +pub type LibosAddress = u64_; +pub const LibosMemoryRegionKind_LIBOS_MEMORY_REGION_NONE: LibosMemoryRegionKind = 0; +pub const LibosMemoryRegionKind_LIBOS_MEMORY_REGION_CONTIGUOUS: LibosMemoryRegionKind = 1; +pub const LibosMemoryRegionKind_LIBOS_MEMORY_REGION_RADIX3: LibosMemoryRegionKind = 2; +pub type LibosMemoryRegionKind = ffi::c_uint; +pub const LibosMemoryRegionLoc_LIBOS_MEMORY_REGION_LOC_NONE: LibosMemoryRegionLoc = 0; +pub const LibosMemoryRegionLoc_LIBOS_MEMORY_REGION_LOC_SYSMEM: LibosMemoryRegionLoc = 1; +pub const LibosMemoryRegionLoc_LIBOS_MEMORY_REGION_LOC_FB: LibosMemoryRegionLoc = 2; +pub type LibosMemoryRegionLoc = ffi::c_uint; +#[repr(C)] +#[derive(Debug, Default, Copy, Clone)] +pub struct LibosMemoryRegionInitArgument { + pub id8: LibosAddress, + pub pa: LibosAddress, + pub size: LibosAddress, + pub kind: u8_, + pub loc: u8_, + pub __bindgen_padding_0: [u8; 6usize], +} -- 2.50.1
