Switch to reg_write and reg_write_mask function pointers for register access, enabling compatibility with platforms regardless of subsys ID support.
Signed-off-by: Jason-JH Lin <[email protected]> --- drivers/gpu/drm/mediatek/mtk_ddp_comp.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c index ac6620e10262..aa217fb11fd7 100644 --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c @@ -72,8 +72,8 @@ void mtk_ddp_write(struct cmdq_pkt *cmdq_pkt, unsigned int value, { #if IS_REACHABLE(CONFIG_MTK_CMDQ) if (cmdq_pkt) - cmdq_pkt_write(cmdq_pkt, cmdq_reg->subsys, - cmdq_reg->offset + offset, value); + cmdq_reg->reg_write(cmdq_pkt, cmdq_reg->subsys, cmdq_reg->pa_base, + cmdq_reg->offset + offset, value); else #endif writel(value, regs + offset); @@ -85,8 +85,8 @@ void mtk_ddp_write_relaxed(struct cmdq_pkt *cmdq_pkt, unsigned int value, { #if IS_REACHABLE(CONFIG_MTK_CMDQ) if (cmdq_pkt) - cmdq_pkt_write(cmdq_pkt, cmdq_reg->subsys, - cmdq_reg->offset + offset, value); + cmdq_reg->reg_write(cmdq_pkt, cmdq_reg->subsys, cmdq_reg->pa_base, + cmdq_reg->offset + offset, value); else #endif writel_relaxed(value, regs + offset); @@ -98,8 +98,8 @@ void mtk_ddp_write_mask(struct cmdq_pkt *cmdq_pkt, unsigned int value, { #if IS_REACHABLE(CONFIG_MTK_CMDQ) if (cmdq_pkt) { - cmdq_pkt_write_mask(cmdq_pkt, cmdq_reg->subsys, - cmdq_reg->offset + offset, value, mask); + cmdq_reg->reg_write_mask(cmdq_pkt, cmdq_reg->subsys, cmdq_reg->pa_base, + cmdq_reg->offset + offset, value, mask); } else { #endif u32 tmp = readl(regs + offset); -- 2.43.0
