Re: [PATCH 04/10] drm/i915/display: Add filter lut values

[Nautiyal, Ankit K]

On 10/1/2025 12:04 PM, Nemesa Garg wrote:

Add the register bits related to filter lut values
and helper to load the casf filter lut.

These values are golden values and these value has
to be loaded one time while enabling the casf.

v2: update commit message[Ankit]
v3: Add intel_casf prefix to filter_load fn[Jani]
v4: Define the filter macros here

Signed-off-by: Nemesa Garg <nemesa.g...@intel.com>

Reviewed-by: Ankit Nautiyal <ankit.k.nauti...@intel.com>

---
  drivers/gpu/drm/i915/display/intel_casf.c     | 49 +++++++++++++++++++
  drivers/gpu/drm/i915/display/intel_casf.h     |  1 +
  .../gpu/drm/i915/display/intel_casf_regs.h    | 11 +++++
  3 files changed, 61 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_casf.c 
b/drivers/gpu/drm/i915/display/intel_casf.c
index ad2faed5c1b3..313ed6b10317 100644
--- a/drivers/gpu/drm/i915/display/intel_casf.c
+++ b/drivers/gpu/drm/i915/display/intel_casf.c
@@ -16,6 +16,13 @@
  #define MAX_PIXELS_FOR_3_TAP_FILTER (1920 * 1080)
  #define MAX_PIXELS_FOR_5_TAP_FILTER (3840 * 2160)

+#define FILTER_COEFF_0_125 125

+#define FILTER_COEFF_0_25 250
+#define FILTER_COEFF_0_5 500
+#define FILTER_COEFF_1_0 1000
+#define FILTER_COEFF_0_0 0
+#define SET_POSITIVE_SIGN(x) ((x) & (~SIGN))
+
  /**
   * DOC: Content Adaptive Sharpness Filter (CASF)
   *
@@ -31,6 +38,46 @@
   * original image.
   */

+/* Default LUT values to be loaded one time. */

+static const u16 sharpness_lut[] = {
+       4095, 2047, 1364, 1022, 816, 678, 579,
+       504, 444, 397, 357, 323, 293, 268, 244, 224,
+       204, 187, 170, 154, 139, 125, 111, 98, 85,
+       73, 60, 48, 36, 24, 12, 0
+};
+
+const u16 filtercoeff_1[] = {
+       FILTER_COEFF_0_0, FILTER_COEFF_0_0, FILTER_COEFF_0_5,
+       FILTER_COEFF_1_0, FILTER_COEFF_0_5, FILTER_COEFF_0_0,
+       FILTER_COEFF_0_0,
+};
+
+const u16 filtercoeff_2[] = {
+       FILTER_COEFF_0_0, FILTER_COEFF_0_25, FILTER_COEFF_0_5,
+       FILTER_COEFF_1_0, FILTER_COEFF_0_5, FILTER_COEFF_0_25,
+       FILTER_COEFF_0_0,
+};
+
+const u16 filtercoeff_3[] = {
+       FILTER_COEFF_0_125, FILTER_COEFF_0_25, FILTER_COEFF_0_5,
+       FILTER_COEFF_1_0, FILTER_COEFF_0_5, FILTER_COEFF_0_25,
+       FILTER_COEFF_0_125,
+};
+
+static void intel_casf_filter_lut_load(struct intel_crtc *crtc,
+                                      const struct intel_crtc_state 
*crtc_state)
+{
+       struct intel_display *display = to_intel_display(crtc_state);
+       int i;
+
+       intel_de_write(display, SHRPLUT_INDEX(crtc->pipe),
+                      INDEX_AUTO_INCR | INDEX_VALUE(0));
+
+       for (i = 0; i < ARRAY_SIZE(sharpness_lut); i++)
+               intel_de_write(display, SHRPLUT_DATA(crtc->pipe),
+                              sharpness_lut[i]);
+}
+
  void intel_casf_update_strength(struct intel_crtc_state *crtc_state)
  {
        struct intel_display *display = to_intel_display(crtc_state);
@@ -115,6 +162,8 @@ void intel_casf_enable(struct intel_crtc_state *crtc_state)
        struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
        u32 sharpness_ctl;

+ intel_casf_filter_lut_load(crtc, crtc_state);

+
        sharpness_ctl = FILTER_EN | 
FILTER_STRENGTH(crtc_state->hw.casf_params.strength);

sharpness_ctl |= crtc_state->hw.casf_params.win_size;

diff --git a/drivers/gpu/drm/i915/display/intel_casf.h 
b/drivers/gpu/drm/i915/display/intel_casf.h
index 753871880279..e8432b4bc52b 100644
--- a/drivers/gpu/drm/i915/display/intel_casf.h
+++ b/drivers/gpu/drm/i915/display/intel_casf.h
@@ -9,6 +9,7 @@
  #include <linux/types.h>

struct intel_crtc_state;

+struct intel_crtc;

int intel_casf_compute_config(struct intel_crtc_state *crtc_state);

  void intel_casf_update_strength(struct intel_crtc_state *new_crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_casf_regs.h 
b/drivers/gpu/drm/i915/display/intel_casf_regs.h
index bd763efe5c1b..87803cca510f 100644
--- a/drivers/gpu/drm/i915/display/intel_casf_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_casf_regs.h
@@ -19,4 +19,15 @@
  #define   SHARPNESS_FILTER_SIZE_5X5   REG_FIELD_PREP(FILTER_SIZE_MASK, 1)
  #define   SHARPNESS_FILTER_SIZE_7X7   REG_FIELD_PREP(FILTER_SIZE_MASK, 2)

+#define _SHRPLUT_DATA_A 0x682B8

+#define _SHRPLUT_DATA_B                        0x68AB8
+#define SHRPLUT_DATA(pipe)             _MMIO_PIPE(pipe, _SHRPLUT_DATA_A, 
_SHRPLUT_DATA_B)
+
+#define _SHRPLUT_INDEX_A               0x682B4
+#define _SHRPLUT_INDEX_B               0x68AB4
+#define SHRPLUT_INDEX(pipe)            _MMIO_PIPE(pipe, _SHRPLUT_INDEX_A, 
_SHRPLUT_INDEX_B)
+#define   INDEX_AUTO_INCR              REG_BIT(10)
+#define   INDEX_VALUE_MASK             REG_GENMASK(4, 0)
+#define   INDEX_VALUE(x)               REG_FIELD_PREP(INDEX_VALUE_MASK, (x))
+
  #endif /* __INTEL_CASF_REGS__ */