Document DSI controller and phy on QCS8300 platform.
Signed-off-by: Ayushi Makhija <quic_amakh...@quicinc.com>
---
.../display/msm/qcom,qcs8300-mdss.yaml | 102 +++++++++++++++++-
1 file changed, 101 insertions(+), 1 deletion(-)
diff --git
a/Documentation/devicetree/bindings/display/msm/qcom,qcs8300-mdss.yaml
b/Documentation/devicetree/bindings/display/msm/qcom,qcs8300-mdss.yaml
index e96baaae9ba9..c41a86203e78 100644
--- a/Documentation/devicetree/bindings/display/msm/qcom,qcs8300-mdss.yaml
+++ b/Documentation/devicetree/bindings/display/msm/qcom,qcs8300-mdss.yaml
@@ -53,13 +53,23 @@ patternProperties:
contains:
const: qcom,qcs8300-dp
+ "^dsi@[0-9a-f]+$":
+ type: object
+ additionalProperties: true
+ properties:
+ compatible:
+ contains:
+ const: qcom,qcs8300-dsi-ctrl
+
"^phy@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
contains:
- const: qcom,qcs8300-edp-phy
+ enum:
+ - qcom,qcs8300-dsi-phy-5nm
+ - qcom,qcs8300-edp-phy
required:
- compatible
@@ -71,6 +81,7 @@ examples:
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,qcs8300-gcc.h>
+ #include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,sa8775p-dispcc.h>
#include <dt-bindings/interconnect/qcom,qcs8300-rpmh.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
@@ -142,6 +153,13 @@ examples:
remote-endpoint = <&mdss_dp0_in>;
};
};
+
+ port@1 {
+ reg = <1>;
+ dpu_intf1_out: endpoint {
+ remote-endpoint = <&mdss_dsi0_in>;
+ };
+ };
};
mdp_opp_table: opp-table {
@@ -169,6 +187,88 @@ examples:
};
};
+ dsi@ae94000 {
+ compatible = "qcom,qcs8300-dsi-ctrl",
+ "qcom,sa8775p-dsi-ctrl",
+ "qcom,mdss-dsi-ctrl";
+ reg = <0x0ae94000 0x400>;
+ reg-names = "dsi_ctrl";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <4>;
+
+ clocks = <&dispcc MDSS_DISP_CC_MDSS_BYTE0_CLK>,
+ <&dispcc MDSS_DISP_CC_MDSS_BYTE0_INTF_CLK>,
+ <&dispcc MDSS_DISP_CC_MDSS_PCLK0_CLK>,
+ <&dispcc MDSS_DISP_CC_MDSS_ESC0_CLK>,
+ <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>;
+ clock-names = "byte",
+ "byte_intf",
+ "pixel",
+ "core",
+ "iface",
+ "bus";
+ assigned-clocks = <&dispcc MDSS_DISP_CC_MDSS_BYTE0_CLK_SRC>,
+ <&dispcc MDSS_DISP_CC_MDSS_PCLK0_CLK_SRC>;
+ assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
+ phys = <&mdss_dsi0_phy>;
+
+ operating-points-v2 = <&dsi0_opp_table>;
+ power-domains = <&rpmhpd RPMHPD_MMCX>;
+
+ vdda-supply = <&vreg_l5a>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ mdss0_dsi0_in: endpoint {
+ remote-endpoint = <&dpu_intf1_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ mdss0_dsi0_out: endpoint { };
+ };
+ };
+
+ dsi0_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-358000000 {
+ opp-hz = /bits/ 64 <358000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+ };
+ };
+
+ mdss_dsi0_phy: phy@ae94400 {
+ compatible = "qcom,qcs8300-dsi-phy-5nm",
+ "qcom,sa8775p-dsi-phy-5nm";
+ reg = <0x0ae94400 0x200>,
+ <0x0ae94600 0x280>,
+ <0x0ae94900 0x27c>;
+ reg-names = "dsi_phy",
+ "dsi_phy_lane",
+ "dsi_pll";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ clocks = <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface", "ref";
+
+ vdds-supply = <&vreg_l4a>;
+ };
+
mdss_dp0_phy: phy@aec2a00 {
compatible = "qcom,qcs8300-edp-phy", "qcom,sa8775p-edp-phy";
--
2.34.1
