The 2 DSI interfaces may be connected to 2 independent panels in bonded-DSI mode. Horizontal timing and DSC configuration are adjusted per individual panel in DSI host side. Support to multiple slice per packet is added for the device setup to test the usage case.
Changes vs v2: - Polish commit message to describe usage case and requirements to panel driver. - Remove changes in device tree and add dual_panel flag in mipi_dsi_device to pass information from panel to dsi host. - Drop the register programming to DSI_VBIF_CTRL, as no issue is seen in latest test. - Link to v2: https://lore.kernel.org/r/20250220-dual-dsi-v2-0-6c0038d5a...@linaro.org Change vs v1: - Add device tree binding for dual panel case in handling frame width for DSC to avoid breaking existing dual-DSI case. - Leverage Marijn's patch to configure proper slice per interface in dsi_update_dsc_timing(). - Polish commit comments. - Link to v1: https://lore.kernel.org/all/20240829-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-8-v1-0-bdb05b4b5...@linaro.org/ Signed-off-by: Jun Nie <jun....@linaro.org> --- Jun Nie (3): drm/msm/dsi: support DSC configurations with slice_per_pkt > 1 drm/mipi-dsi: Add flag to support dual-panel configurations drm/msm/dsi: Support dual panel use case with single CRTC drivers/gpu/drm/msm/dsi/dsi_host.c | 35 +++++++++++++++++++---------------- include/drm/drm_mipi_dsi.h | 4 ++++ 2 files changed, 23 insertions(+), 16 deletions(-) --- base-commit: a3306041f55d0f86c40d06eaad1d4e8f06e4483d change-id: 20250924-dsi-dual-panel-upstream-4aded63bd2d5 Best regards, -- Jun Nie <jun....@linaro.org>
