Introduce TXVMPSPHSETR_DT_MASK macro and use FIELD_PREP() to generate appropriate bitfield from mask and value without bitshift.
Do not convert bits and bitfields to BIT() and GENMASK() yet, to be consisten with the current style. Conversion to BIT() and GENMASK() macros is done at the very end of this series in the last two patches. Signed-off-by: Marek Vasut <marek.vasut+rene...@mailbox.org> --- Cc: David Airlie <airl...@gmail.com> Cc: Geert Uytterhoeven <geert+rene...@glider.be> Cc: Kieran Bingham <kieran.bingham+rene...@ideasonboard.com> Cc: Laurent Pinchart <laurent.pinchart+rene...@ideasonboard.com> Cc: Maarten Lankhorst <maarten.lankho...@linux.intel.com> Cc: Magnus Damm <magnus.d...@gmail.com> Cc: Maxime Ripard <mrip...@kernel.org> Cc: Simona Vetter <sim...@ffwll.ch> Cc: Thomas Zimmermann <tzimmerm...@suse.de> Cc: Tomi Valkeinen <tomi.valkeinen+rene...@ideasonboard.com> Cc: dri-devel@lists.freedesktop.org Cc: linux-renesas-...@vger.kernel.org --- NOTE: No functional change expected, this is a preparatory patch which partly removes macros which evaluate to zeroes from rcar_mipi_dsi_regs.h . The other patches in this series proceed with that job, piece by piece, to make it all reviewable. --- V2: Move FIELD_PREP() back into rcar_mipi_dsi_regs.h --- drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h b/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h index 850f8e214a964..7c828f46cbb76 100644 --- a/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h +++ b/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h @@ -168,11 +168,12 @@ #define TXVMSCR_STR (1 << 16) #define TXVMPSPHSETR 0x1c0 -#define TXVMPSPHSETR_DT_RGB16 (0x0e << 16) -#define TXVMPSPHSETR_DT_RGB18 (0x1e << 16) -#define TXVMPSPHSETR_DT_RGB18_LS (0x2e << 16) -#define TXVMPSPHSETR_DT_RGB24 (0x3e << 16) -#define TXVMPSPHSETR_DT_YCBCR16 (0x2c << 16) +#define TXVMPSPHSETR_DT_MASK (0x3f << 16) +#define TXVMPSPHSETR_DT_RGB16 FIELD_PREP(TXVMPSPHSETR_DT_MASK, 0x0e) +#define TXVMPSPHSETR_DT_RGB18 FIELD_PREP(TXVMPSPHSETR_DT_MASK, 0x1e) +#define TXVMPSPHSETR_DT_RGB18_LS FIELD_PREP(TXVMPSPHSETR_DT_MASK, 0x2e) +#define TXVMPSPHSETR_DT_RGB24 FIELD_PREP(TXVMPSPHSETR_DT_MASK, 0x3e) +#define TXVMPSPHSETR_DT_YCBCR16 FIELD_PREP(TXVMPSPHSETR_DT_MASK, 0x2c) #define TXVMVPRMSET0R 0x1d0 #define TXVMVPRMSET0R_HSPOL_HIG (0 << 17) -- 2.51.0
