Re: [PATCH v2 1/4] clk: tegra20: reparent dsi clock to pll_d_out0

[Stephen Boyd]

Quoting Svyatoslav Ryhel (2025-09-06 06:16:52)
> Reparent DSI clock to PLLD_OUT0 instead of directly descend from PLLD.
> 
> Signed-off-by: Svyatoslav Ryhel <clamo...@gmail.com>
> ---

Acked-by: Stephen Boyd <sb...@kernel.org>