In the GC620 on T-Head TH1520 SoC, the SECURITY feature flag isn't set but the SECURITY_AHB feature flag is set.
In this situation, the VIVS_MMUv2_AHB_CONTROL register isn't available, but the GPU otherwise behave like secure ones and require commands to load PTA. The 6.4.6.9.354872 driver from T-Head asserts SECURITY_AHB feature flag is set when SECURITY one is set, so it could be assumed that the situation that only SECURITY is set do not exist. Signed-off-by: Icenowy Zheng <[email protected]> --- No changes in v2. drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c index cf0d9049bcf1e..7431e180b3ae4 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c +++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c @@ -559,7 +559,7 @@ static int etnaviv_hw_reset(struct etnaviv_gpu *gpu) control |= VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU; gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); - if (gpu->sec_mode == ETNA_SEC_KERNEL) { + if (gpu->identity.minor_features7 & chipMinorFeatures7_BIT_SECURITY) { gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL, VIVS_MMUv2_AHB_CONTROL_RESET); } else { @@ -797,7 +797,7 @@ static void etnaviv_gpu_hw_init(struct etnaviv_gpu *gpu) gpu_write(gpu, VIVS_MC_BUS_CONFIG, bus_config); } - if (gpu->sec_mode == ETNA_SEC_KERNEL) { + if (gpu->identity.minor_features7 & chipMinorFeatures7_BIT_SECURITY) { u32 val = gpu_read(gpu, VIVS_MMUv2_AHB_CONTROL); val |= VIVS_MMUv2_AHB_CONTROL_NONSEC_ACCESS; gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL, val); @@ -853,7 +853,7 @@ int etnaviv_gpu_init(struct etnaviv_gpu *gpu) * On cores with security features supported, we claim control over the * security states. */ - if ((gpu->identity.minor_features7 & chipMinorFeatures7_BIT_SECURITY) && + if ((gpu->identity.minor_features7 & chipMinorFeatures7_BIT_SECURITY) || (gpu->identity.minor_features10 & chipMinorFeatures10_SECURITY_AHB)) gpu->sec_mode = ETNA_SEC_KERNEL; -- 2.51.0
