On Wed, Sep 03, 2025 at 02:26:30PM +0200, Konrad Dybcio wrote:
> On 8/21/25 8:55 PM, Akhil P Oommen wrote:
> > From: Puranam V G Tejaswi <[email protected]>
> >
> > Add gpu and gmu nodes for sa8775p chipset. As of now all
> > SKUs have the same GPU fmax, so there is no requirement of
> > speed bin support.
> >
> > Signed-off-by: Puranam V G Tejaswi <[email protected]>
> > Signed-off-by: Akhil P Oommen <[email protected]>
> > Reviewed-by: Dmitry Baryshkov <[email protected]>
> > ---
> > arch/arm64/boot/dts/qcom/lemans.dtsi | 116
> > +++++++++++++++++++++++++++++++++++
> > 1 file changed, 116 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi
> > b/arch/arm64/boot/dts/qcom/lemans.dtsi
> > index
> > 8ceb59742a9fc6562b2c38731ddabe3a549f7f35..8eac8d4719db9230105ad93ac22287850b6b007c
> > 100644
> > --- a/arch/arm64/boot/dts/qcom/lemans.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi
> > @@ -1097,6 +1097,18 @@ ipcc: mailbox@408000 {
> > #mbox-cells = <2>;
> > };
> >
> > + qfprom: efuse@784000 {
> > + compatible = "qcom,sa8775p-qfprom", "qcom,qfprom";
> > + reg = <0x0 0x00784000 0x0 0x2410>;
>
> len = 0x3000
>
> [...]
>
> > + gmu: gmu@3d6a000 {
> > + compatible = "qcom,adreno-gmu-663.0", "qcom,adreno-gmu";
> > + reg = <0x0 0x03d6a000 0x0 0x34000>,
>
> This bleeds into GPU_CC, len should be 0x26000
gpucc is in the middle of GMU, see other platforms.
>
> > + <0x0 0x03de0000 0x0 0x10000>,
> > + <0x0 0x0b290000 0x0 0x10000>;
> > + reg-names = "gmu", "rscc", "gmu_pdc";
> > + interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupt-names = "hfi", "gmu";
> > + clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
> > + <&gpucc GPU_CC_CXO_CLK>,
> > + <&gcc GCC_DDRSS_GPU_AXI_CLK>,
> > + <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
> > + <&gpucc GPU_CC_AHB_CLK>,
> > + <&gpucc GPU_CC_HUB_CX_INT_CLK>,
> > + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
>
> This clock only belongs in the SMMU node
>
> > + clock-names = "gmu",
> > + "cxo",
> > + "axi",
> > + "memnoc",
> > + "ahb",
> > + "hub",
> > + "smmu_vote";
> > + power-domains = <&gpucc GPU_CC_CX_GDSC>,
> > + <&gpucc GPU_CC_GX_GDSC>;
> > + power-domain-names = "cx",
> > + "gx";
> > + iommus = <&adreno_smmu 5 0xc00>;
> > + operating-points-v2 = <&gmu_opp_table>;
> > +
> > + gmu_opp_table: opp-table {
> > + compatible = "operating-points-v2";
> > +
> > + opp-200000000 {
> > + opp-hz = /bits/ 64 <200000000>;
>
> 500 MHz @ RPMH_REGULATOR_LEVEL_SVS, 200 isn't even present in the clock driver
>
> Konrad
--
With best wishes
Dmitry
