On Mon, 28 Jul 2025 at 22:28, Lad, Prabhakar <[email protected]> wrote: > On Mon, Jul 28, 2025 at 9:14 PM Prabhakar <[email protected]> wrote: > > From: Lad Prabhakar <[email protected]> > > > > Add the compatible string "renesas,r9a09g057-mipi-dsi" for the Renesas > > RZ/V2H(P) (R9A09G057) SoC. While the MIPI DSI LINK registers are shared > > with the RZ/G2L SoC, the D-PHY register layout differs. Additionally, the > > RZ/V2H(P) uses only two resets compared to three on RZ/G2L, and requires > > five clocks instead of six. > > > > To reflect these hardware differences, update the binding schema to > > support the reduced clock and reset requirements for RZ/V2H(P). > > > > Since the RZ/V2N (R9A09G056) SoC integrates an identical DSI IP to > > RZ/V2H(P), the same "renesas,r9a09g057-mipi-dsi" compatible string is > > reused for RZ/V2N. > > > > Signed-off-by: Lad Prabhakar <[email protected]> > > Reviewed-by: Krzysztof Kozlowski <[email protected]> > > Reviewed-by: Geert Uytterhoeven <[email protected]> > > --- > > v6->v7: > > - Renamed pllclk to pllrefclk > > - Preserved the reviewed by tag from Geert and Krzysztof > > > - Included support for RZ/V2N in the same patch > - Updated commit description. > > I missed mentioning the above.
Reviewed-by: Geert Uytterhoeven <[email protected]> Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected] In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
