On Thu, Jul 31, 2025 at 11:50:16AM +0200, Louis Chauvet wrote:
>
>
> Le 31/07/2025 à 02:17, Rob Herring a écrit :
> > On Wed, Jul 30, 2025 at 07:02:46PM +0200, Louis Chauvet wrote:
> > > For am62 processors, we need to use the newly created clk-ctrl property to
> > > properly handle data edge sampling configuration. Add them in the main
> > > device tree.
> > >
> > > Fixes: 32a1795f57ee ("drm/tidss: New driver for TI Keystone platform
> > > Display SubSystem")
> > > Signed-off-by: Louis Chauvet <[email protected]>
> > > ---
> > >
> > > Cc: [email protected]
> > > ---
> > > arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 6 ++++++
> > > 1 file changed, 6 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi
> > > b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi
> > > index
> > > 9e0b6eee9ac77d66869915b2d7bec3e2275c03ea..d3131e6da8e70fde035d3c44716f939e8167795a
> > > 100644
> > > --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi
> > > +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi
> > > @@ -76,6 +76,11 @@ audio_refclk1: clock-controller@82e4 {
> > > assigned-clock-parents = <&k3_clks 157 18>;
> > > #clock-cells = <0>;
> > > };
> > > +
> > > + dss_clk_ctrl: dss_clk_ctrl@8300 {
> > > + compatible = "ti,am625-dss-clk-ctrl", "syscon";
> > > + reg = <0x8300 0x4>;
> >
> > H/w blocks are rarely only 4 bytes of registers... Does this belong to
> > some larger block. The problem with bindings defining single registers
> > like this is they don't get defined until needed and you have a constant
> > stream of DT updates.
>
> In this case, I don't think there is a "larger block". This register exists
> only because TI had issues in the display controller [1].
>
> Here is the extract of MMR registers ([2], page 4311):
>
> [...]
> A2E4h AUDIO_REFCLK1_CTRL_PROXY <unrelated>
Here is clk ctrl proxy...
> A300h DPI0_CLK_CTRL_PROXY <this register, 32 bits>
and here as well, so pretty related. This looks also close to regular
syscon and we do not define individual syscon registers as device nodes.
Best regards,
Krzysztof
