On 7/23/2025 3:57 PM, Konrad Dybcio wrote: > On 7/22/25 11:27 PM, Akhil P Oommen wrote: >> On 7/22/2025 7:19 PM, Dmitry Baryshkov wrote: >>> On Sun, Jul 20, 2025 at 05:46:12PM +0530, Akhil P Oommen wrote: >>>> Add a new quirk to denote IFPC (Inter-Frame Power Collapse) support >>>> for a gpu. Based on this flag send the feature ctrl hfi message to >>>> GMU to enable IFPC support. >>>> >>>> Signed-off-by: Akhil P Oommen <[email protected]> >>>> --- > > [...] > >>>> +static int a6xx_hfi_enable_ifpc(struct a6xx_gmu *gmu) >>>> +{ >>>> + if (gmu->idle_level != GMU_IDLE_STATE_IFPC) >>>> + return 0; >>>> + >>>> + return a6xx_hfi_feature_ctrl_msg(gmu, HFI_FEATURE_IFPC, 1, 0x1680); >>> >>> magic number? >>> >> >> Let me check. > > techpack-graphics/adreno_a6xx_gmu.c: > 537:#define A6X_GMU_LONG_IFPC_HYST FIELD_PREP(GENMASK(15, 0), 0x1680) > 541:#define A6X_GMU_LONG_IFPC_HYST_FLOOR FIELD_PREP(GENMASK(15, 0), > 0x0F00) > > (same value for a7/a8) > > 0x0f00 is 3840, which smells oddly like the XO clock rate (possibly mul/div2) > > (38.4 MHz or 19.2) / 3840 is (1000 or 500) (ms? us? cycles?) and the other > one is > (333 or 667) - without any further information I'd estimate this is some sort > of > scheduler tuning
Thats right. It is around 300us. Will add the same macro in the next rev. -Akhil > > Konrad
