From: "shangyao.lin" <[email protected]> 1. Add camera isp7x module device document
--- Changes in v2: - Rename binding file to mediatek,mt8188-seninf-core.yaml - Various fixes per review comments - Update maintainers list Question for reviewer (CK): Hi CK, Thank you for your review and suggestions on this patch, especially for providing the reference patch (https://patchwork.kernel.org/project/linux-mediatek/list/?series=874617) and for mentioning in another patch ([V1,02/10] MEDIA: PLATFORM: MEDIATEK: ADD SENINF CONTROLLER) the suggestion to "Move the phy part to phy/mediatek/ folder. You could refer to phy/mediatek/phy-mtk-mipi-csi-0-5.c". After reading your comments and the reference patches, my understanding is that only the seninf-core driver should manage all ports internally, and each port corresponds to a PHY. During probe, the driver will parse each port, obtain the corresponding PHY (e.g., devm_phy_get(dev, "csi0"), devm_phy_get(dev, "csi1"), etc.), and operate the PHY for each port individually during stream on/off or power on/off. Could you please confirm if my understanding is correct? If you have any additional reference patches or examples, I would greatly appreciate it. Thank you for your guidance! Best regards, Shangyao Signed-off-by: shangyao.lin <[email protected]> --- .../mediatek/mediatek,mt8188-seninf-core.yaml | 121 ++++++++++++++++++ 1 file changed, 121 insertions(+) create mode 100755 Documentation/devicetree/bindings/media/mediatek/mediatek,mt8188-seninf-core.yaml diff --git a/Documentation/devicetree/bindings/media/mediatek/mediatek,mt8188-seninf-core.yaml b/Documentation/devicetree/bindings/media/mediatek/mediatek,mt8188-seninf-core.yaml new file mode 100755 index 000000000000..763b96b561cf --- /dev/null +++ b/Documentation/devicetree/bindings/media/mediatek/mediatek,mt8188-seninf-core.yaml @@ -0,0 +1,121 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (c) 2023 MediaTek Inc. +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/media/mediatek,seninf-core.yaml#"; +$schema: "http://devicetree.org/meta-schemas/core.yaml#"; + +title: The seninf-core top unit of MediaTek ISP system + +maintainers: + - Shangyao Lin <[email protected]> + - Shu-hsiang Yang <[email protected]> + - Shun-yi Wang <[email protected]> + - Teddy Chen <[email protected]> + +description: | + MediaTek seninf-core is the ISP sensor interface unit in MediaTek SoC. + The sensor interface serves as the MIPI-CSI2 top RX controller. + +properties: + compatible: + const: mediatek,mt8188-seninf-core + + reg: + minItems: 1 + maxItems: 1 + description: | + Base address register region. + + reg-names: + items: + - const: base + minItems: 1 + maxItems: 1 + + mtk_csi_phy_ver: + description: Describes MediaTek camera Rx controller version + $ref: /schemas/types.yaml#/definitions/string + + interrupts: + minItems: 1 + maxItems: 2 + + power-domains: + minItems: 1 + maxItems: 4 + + clocks: + minItems: 4 + maxItems: 4 + description: List of clock phandles required by the controller. + + clock-names: + items: + - const: clk_cam_seninf + - const: clk_top_seninf + - const: clk_top_seninf1 + - const: clk_top_camtm + minItems: 4 + maxItems: 4 + + mediatek,larbs: + description: | + List of phandles to the local arbiters in the current SoCs. + Refer to bindings/memory-controllers/mediatek,smi-larb.yaml. + $ref: /schemas/types.yaml#/definitions/phandle-array + minItems: 1 + maxItems: 32 + + dma-ranges: + description: | + Describes the address information of IOMMU mapping to memory. + Defines six fields for the MediaTek IOMMU extended iova, pa, and size. + minItems: 1 + + phys: + description: List of phandle and args to the PHY provider. + $ref: /schemas/types.yaml#/definitions/phandle-array + + phy-names: + description: Names of the PHYs. + $ref: /schemas/types.yaml#/definitions/string-array + +required: + - compatible + - reg + - reg-names + - interrupts + - power-domains + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/power/mediatek,mt8188-power.h> + #include <dt-bindings/clock/mediatek,mt8188-clk.h> + + seninf@16010000 { + compatible = "mediatek,mt8188-seninf-core"; + reg = <0 0x16010000 0 0x8000>; + reg-names = "base"; + mtk_csi_phy_ver = "mtk_csi_phy_2_0"; + interrupts = <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8188_POWER_DOMAIN_CSIRX_TOP>, + <&spm MT8188_POWER_DOMAIN_CAM_VCORE>, + <&spm MT8188_POWER_DOMAIN_CAM_MAIN>; + clocks = <&camsys CLK_CAM_MAIN_SENINF>, + <&topckgen CLK_TOP_SENINF>, + <&topckgen CLK_TOP_SENINF1>, + <&topckgen CLK_TOP_CAMTM>; + clock-names = "clk_cam_seninf", + "clk_top_seninf", + "clk_top_seninf1", + "clk_top_camtm"; + }; + +... \ No newline at end of file -- 2.18.0
