On Thu, Feb 27, 2025 at 05:58:01PM +0100, Marek Vasut wrote:
> The instance of the GPU populated in Freescale i.MX95 does require
> release from reset by writing into a single GPUMIX block controller
> GPURESET register bit 0. Document support for this reset register.
>
> Signed-off-by: Marek Vasut <[email protected]>
> ---
> Cc: Boris Brezillon <[email protected]>
> Cc: Conor Dooley <[email protected]>
> Cc: David Airlie <[email protected]>
> Cc: Fabio Estevam <[email protected]>
> Cc: Krzysztof Kozlowski <[email protected]>
> Cc: Liviu Dudau <[email protected]>
> Cc: Maarten Lankhorst <[email protected]>
> Cc: Maxime Ripard <[email protected]>
> Cc: Pengutronix Kernel Team <[email protected]>
> Cc: Philipp Zabel <[email protected]>
> Cc: Rob Herring <[email protected]>
> Cc: Sascha Hauer <[email protected]>
> Cc: Sebastian Reichel <[email protected]>
> Cc: Shawn Guo <[email protected]>
> Cc: Simona Vetter <[email protected]>
> Cc: Steven Price <[email protected]>
> Cc: Thomas Zimmermann <[email protected]>
> Cc: [email protected]
> Cc: [email protected]
> Cc: [email protected]
> Cc: [email protected]
> ---
> .../reset/fsl,imx95-gpu-blk-ctrl.yaml | 49 +++++++++++++++++++
> 1 file changed, 49 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/reset/fsl,imx95-gpu-blk-ctrl.yaml
>
> diff --git
> a/Documentation/devicetree/bindings/reset/fsl,imx95-gpu-blk-ctrl.yaml
> b/Documentation/devicetree/bindings/reset/fsl,imx95-gpu-blk-ctrl.yaml
> new file mode 100644
> index 0000000000000..dc701bd556c0b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/reset/fsl,imx95-gpu-blk-ctrl.yaml
> @@ -0,0 +1,49 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/reset/fsl,imx95-gpu-blk-ctrl.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Freescale i.MX95 GPU Block Controller
> +
> +maintainers:
> + - Marek Vasut <[email protected]>
> +
> +description: |
Needn't |
> + This reset controller is a block of ad-hoc debug registers, one of
> + which is a single-bit GPU reset.
> +
> +properties:
> + compatible:
> + - const: fsl,imx95-gpu-blk-ctrl
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + maxItems: 1
> +
> + power-domains:
> + maxItems: 1
> +
> + '#reset-cells':
> + const: 1
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - power-domains
> + - '#reset-cells'
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + reset-controller@4d810000 {
> + compatible = "fsl,imx95-gpu-blk-ctrl";
> + reg = <0x0 0x4d810000 0x0 0xc>;
No sure if it pass dt_binding_check, I remember default 32bit address
reg = <0x4d810000 0xc>
> + clocks = <&scmi_clk IMX95_CLK_GPUAPB>;
suppose you missed dt-binding include file for IMX95_CLK_GPUAPB
Frank
> + power-domains = <&scmi_devpd IMX95_PD_GPU>;
> + #reset-cells = <1>;
> + };
> --
> 2.47.2
>
