VOP2 on RK3588 is able to use the HDMI PHY PLL as an alternative and more accurate pixel clock source to improve handling of display modes up to 4K@60Hz on video ports 0, 1 and 2.
For now only HDMI0 output is supported, hence add the related PLL clock. Tested-by: FUKAUMI Naoki <[email protected]> Signed-off-by: Cristian Ciocaltea <[email protected]> --- arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi index 22462e86f48027ab7c5e270f2fa04df7afcc1d24..d07be2a81f28b4cbfe314992c662d8cfb3d3d344 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi @@ -1262,14 +1262,16 @@ vop: vop@fdd90000 { <&cru DCLK_VOP1>, <&cru DCLK_VOP2>, <&cru DCLK_VOP3>, - <&cru PCLK_VOP_ROOT>; + <&cru PCLK_VOP_ROOT>, + <&hdptxphy_hdmi0>; clock-names = "aclk", "hclk", "dclk_vp0", "dclk_vp1", "dclk_vp2", "dclk_vp3", - "pclk_vop"; + "pclk_vop", + "pll_hdmiphy0"; iommus = <&vop_mmu>; power-domains = <&power RK3588_PD_VOP>; rockchip,grf = <&sys_grf>; -- 2.47.0
