On Mon, Oct 14, 2024 at 03:19:42PM +0530, Manikandan Muralidharan wrote: > From: Cyrille Pitchen <[email protected]> > > On SoCs, like the SAM9X75, which embed the XLCDC ip, the registers that > configure the unified scaling engine were not filled with proper values. > > Indeed, for YCbCr formats, the VXSCFACT bitfield of the HEOCFG25 > register and the HXSCFACT bitfield of the HEOCFG27 register were > incorrect. > > For 4:2:0 formats, both vertical and horizontal factors for > chroma chanels should be divided by 2 from the factors for the luma > channel. Hence: > > HEOCFG24.VXSYFACT = VFACTOR > HEOCFG25.VSXCFACT = VFACTOR / 2 > HEOCFG26.HXSYFACT = HFACTOR > HEOCFG27.HXSCFACT = HFACTOR / 2 > > However, for 4:2:2 formats, only the horizontal factor for chroma > chanels should be divided by 2 from the factor for the luma channel; > the vertical factor is the same for all the luma and chroma channels. > Hence: > > HEOCFG24.VXSYFACT = VFACTOR > HEOCFG25.VXSCFACT = VFACTOR > HEOCFG26.HXSYFACT = HFACTOR > HEOCFG27.HXSCFACT = HFACTOR / 2 > > Fixes: d498771b0b83 ("drm: atmel_hlcdc: Add support for XLCDC using IP > specific driver ops") > Signed-off-by: Cyrille Pitchen <[email protected]> > --- > .../gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c | 27 ++++++++++++++++--- > 1 file changed, 24 insertions(+), 3 deletions(-) >
Reviewed-by: Dmitry Baryshkov <[email protected]> -- With best wishes Dmitry
