Am Sonntag, 23. Juni 2024, 16:38:37 CEST schrieb Marek Vasut: > The only information in the datasheet regarding this divider is a note > in SYS_PLLPARAM register documentation which states that when LSCLK is > 270 MHz, LSCLK_DIV should be 1. What should LSCLK_DIV be set to when > LSCLK is 162 MHz (for DP 1.62G mode) is unclear, but empirical test > confirms using LSCLK_DIV 1 has no adverse effects either. In the worst > case, the internal TC358767 clock would run faster. > > Signed-off-by: Marek Vasut <[email protected]>
Works also on a 2.7Gbps link. Reviewed-by: Alexander Stein <[email protected]> > --- > Cc: Andrzej Hajda <[email protected]> > Cc: Daniel Vetter <[email protected]> > Cc: David Airlie <[email protected]> > Cc: Jernej Skrabec <[email protected]> > Cc: Jonas Karlman <[email protected]> > Cc: Laurent Pinchart <[email protected]> > Cc: Lucas Stach <[email protected]> > Cc: Maarten Lankhorst <[email protected]> > Cc: Maxime Ripard <[email protected]> > Cc: Neil Armstrong <[email protected]> > Cc: Robert Foss <[email protected]> > Cc: Thomas Zimmermann <[email protected]> > Cc: [email protected] > Cc: [email protected] > --- > V2: No change > V3: No change > --- > drivers/gpu/drm/bridge/tc358767.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/bridge/tc358767.c > b/drivers/gpu/drm/bridge/tc358767.c > index a48454fe2f634..743bf1334923d 100644 > --- a/drivers/gpu/drm/bridge/tc358767.c > +++ b/drivers/gpu/drm/bridge/tc358767.c > @@ -738,7 +738,7 @@ static int tc_stream_clock_calc(struct tc_data *tc) > static int tc_set_syspllparam(struct tc_data *tc) > { > unsigned long rate; > - u32 pllparam = SYSCLK_SEL_LSCLK | LSCLK_DIV_2; > + u32 pllparam = SYSCLK_SEL_LSCLK | LSCLK_DIV_1; > > rate = clk_get_rate(tc->refclk); > switch (rate) { > -- TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany Amtsgericht München, HRB 105018 Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider http://www.tq-group.com/
